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Data Sheet July 2001
L9311 Line Interface and Line Access Circuit Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Introduction
The Agere Systems Inc. L9311 is a combination fullfeature, ultralow-power SLIC, solid-state ringing access relay, and line test matrix. It is part of a pinfor-pin compatible family of devices designed to serve a wide variety of applications. The L9311 is optimized for North American access applications where TR-57 longitudinal balance and GR-909 line test are required.
Applications
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Pair Gain Digital Loop Carrier (DLC) Central Office (CO) Fiber-in-the-Loop (FITL)
Description
The L9311 electronic line interface and line access circuit (LILAC) provides all the functions that are necessary to interface a codec to the tip and ring of a subscriber loop, integrating the battery feed and ringing access relay and line test access in one lowpower, low-cost package. The L9311 requires a 5 V and battery supply to operate. Included is an automatic battery switch. The battery feed offers forward and reverse battery, on-hook transmission, and ground start operational modes. It also has a low-power scan and a disconnect mode. In all operating states, this IC is designed for minimal power dissipation. This device is designed to minimize the number of external components required at all interfaces. The dc template, current limit, and overhead voltage and loop supervision threshold are programmable via an applied voltage source. The voltage source may be an external programmable voltage source or derived from the VREF SLIC output. The integrated solid-state switch offers power ringing access. Impulse noise is minimized, thus eliminating the need for external zero-cross switching circuitry. The L9311 provides line test capability, consistent with GR-909 requirements. The differential or singleended ac and dc line voltage or current may be measured by the L9311.
Features
SLIC
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5 V and battery operation Optional automatic battery switch 13 operational and test modes Appropriate for 58 dB longitudinal balance applications Minimal external components required at all interfaces Ultralow power dissipation Software/hardware adjustable dc parameters and supervision thresholds Ground start
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Solid-State Ring Relay
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Low impulse noise Current-limited switches/thermal protection
Line Test Matrix
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GR-909 test capability Single-ended or differential measurements Current or voltage sense ac or dc measurements Dedicated analog input and output
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Table of Contents
Contents Page Contents Page
Introduction..................................................................1 Features ....................................................................1 SLIC .......................................................................1 Solid-State Ring Relay ...........................................1 Line Test Matrix......................................................1 Applications...............................................................1 Description ................................................................1 Features ......................................................................4 Description...................................................................4 Architecture .................................................................8 Pin Information ............................................................9 Operating States........................................................11 Input State Coding ..................................................11 State Definitions ........................................................13 Primary Control Modes ...........................................13 Powerup, Forward Battery....................................13 Powerup, Reverse Battery ...................................13 Scan .....................................................................13 Ground Start.........................................................13 Ringing .................................................................13 Disconnect--Break Before Make .........................14 Tip Amp ................................................................14 Ring Amp .............................................................14 Tip and Ring Amp.................................................14 Reset ....................................................................14 Secondary Control Mode States .............................14 Voltage: Tip to Ground .........................................14 Voltage: Ring to Ground.......................................14 Voltage: Tip to Ring..............................................14 Current: Tip to Ring--VTX ...................................14 Current: Tip to Ring--VITR ..................................15 Reference Voltage ...............................................15 TEST Off ..............................................................15 Special States .........................................................15 Thermal Shutdown ...............................................15 Battery Out of Range ...........................................15 Absolute Maximum Ratings.......................................16 Electrical Characteristics ...........................................17 Ring Trip Detector ...................................................18 Test ........................................................................19 SLIC Two-Wire Port ................................................20 Analog Pin Characteristics ......................................21 ac Feed Characteristics ..........................................22 Logic Inputs and Outputs, VDD = 5.0 V ...................23 Timing Requirements ..............................................23 Switch Characteristics.............................................24 On-State Switch I-V Characteristics........................25 Test Configurations ...................................................26
Applications .............................................................. 28 dc Characteristics................................................... 28 Power Control...................................................... 28 Power Derating.................................................... 28 Automatic Battery Switch .................................... 29 Power Control Resistor ....................................... 29 Overhead Voltage ............................................... 30 dc Loop Current Limit .......................................... 31 Loop Range......................................................... 31 Battery Feed ........................................................ 32 Battery Reversal Rate ......................................... 33 Longitudinal to Metallic Balance.......................... 33 Supervision ............................................................... 33 Loop Closure.......................................................... 33 Ring Trip ................................................................ 34 Ring Ground Detector ............................................ 34 Switching Behavior................................................. 34 Make-Before-Break Operation ............................... 34 Break-Before-Make Operation ............................... 35 Protection ................................................................. 35 External Protection................................................. 35 Active Mode Response at PT/PR........................... 36 Ring Mode Response at PT/PR ............................. 37 Internal Tertiary Protection..................................... 37 Diode Bridge........................................................ 37 Battery Out of Range Detector: High (Magnitude) ................................................. 37 Battery Out of Range Detector: Low (Magnitude) ................................................. 37 Special Functions ..................................................... 38 Line Test ................................................................ 38 ac Applications ......................................................... 40 ac Parameters........................................................ 40 Codec Types .......................................................... 40 ac Interface Network .............................................. 41 Design Tools .......................................................... 42 First-Generation Codec ac Interface Network........ 42 First-Generation Codec ac Interface Network: Resistive Termination ................... 42 Example 1, Real Termination .............................. 43 Third-Generation Codec ac Interface Network: Complex Termination ................... 46 Outline Diagram........................................................ 48 44-Pin PLCC .......................................................... 48 Ordering Information................................................. 49
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Table of Contents (continued)
Figures Page Tables Page
Figure 1. Architecture Diagram................................... 8 Figure 2. Test Diagram............................................... 9 Figure 3. 44-Pin PLCC ............................................... 9 Figure 4. Timing Requirements ................................ 23 Figure 5. On-State I-V Characteristics...................... 25 Figure 6. Basic Test Circuit ...................................... 26 Figure 7. Metallic PSRR ........................................... 27 Figure 8. Longitudinal PSRR .................................... 27 Figure 9. Longitudinal Balance ................................. 27 Figure 10. Longitudinal Impedance .......................... 27 Figure 11. ac Gains .................................................. 27 Figure 12. L9311 Loop/Battery Current (with Battery Switch) vs. Loop Resistance ....... 29 Figure 13. Tip/Ring Voltage ..................................... 32 Figure 14. L9311 Loop Current vs. Loop Voltage..... 32 Figure 15. ac Equivalent Circuit................................ 43 Figure 16. Agere T7504 First-Generation Codec Resistive Termination, Single Battery Operation................................................. 44 Figure 17. L9311 for Agere T8536 Third-Generation Codec, Dual Battery Operation, ac and dc Parameters, Fully Programmable............ 46
Table 1. Pin Descriptions ........................................... 9 Table 2. Primary Control States................................ 12 Table 3. Secondary Control States ........................... 12 Table 4. Supervision Coding..................................... 12 Table 5. Device Operating Conditions and Powering ..................................................... 17 Table 6. Ring Trip Detector ....................................... 18 Table 7. ac Test Source ............................................ 19 Table 8. Test Sense .................................................. 19 Table 9. SLIC Two-Wire Port .................................... 20 Table 10. Analog Pin Characteristics ........................ 21 Table 11. ac Feed Characteristics............................. 22 Table 12. Logic Inputs and Outputs .......................... 23 Table 13. Timing Requirements ................................ 23 Table 14. Break Switches (SW1, 2) .......................... 24 Table 15. Ring Return Switch (SW3) ........................ 24 Table 16. Ringing Access Switch (SW4) .................. 25 Table 17. Typical Active Mode On- to Off-Hook Tip/Ring Current-Limit Transient Response .................................................. 31 Table 18. FB1 and FB2 Values vs. Typical Ramp Time .......................................................... 33 Table 19. Break-Before-Make Logic Control Sequence Device Switching...................... 35 Table 20. TESTLEV Output Options......................... 39 Table 21. L9311 Parts List for Agere T7504 First-Generation Codec, Resistive Termination, Single Battery Operation ................... 45 Table 22. L9311 Parts List for Agere T8536 Third-Generation Codec, Dual Battery Operation, ac and dc Parameters, Fully Programmable........................................... 47
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Features
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SLIC, solid-state ring relay, and line test access, integrated into a single package 5 V and battery operation User-defined power control options: -- Automatic battery switch -- Power control resistor -- Package thermal capabilities Minimal external components required Operating states: -- Forward active -- Reverse active (controlled rate of reversal) -- Scan -- Ground start (tip open) -- All-off or disconnect -- Ring -- Line test modes (dc/ac line voltage/current) Ultralow power: -- Scan, 15 mW -- Active states, on-hook, 75 mW -- Ring mode, on-hook, 90 mW -- Disconnect, 10 mW Adjustable overhead voltage: -- Default overhead adequate for 3.14 dB into 900 overload -- Controlled rate of overhead adjustment Latched parallel input data interface with reset Interrupt (unlatched) based loop status monitor Adjustable current limiter: -- 10 mA to 45 mA programming range Adjustable loop closure detector with hysteresis: -- 4 mA detect, 2.5 mA no detect minimum, upper limit of 15 mA detect -- Hysteresis, typical 20% of programmed on-hook to off-hook threshold Ring trip detector: -- Single-pole filtering Thermal shutdown protection with hysteresis Line break switch will foldover into a low-current state under high-voltage fault conditions Battery out-of-range monitor circuit: -- All-off upon loss of battery (low battery condition) -- All-off upon high battery (fault condition) Longitudinal balance: -- TR-57 balance
Ground start: -- Tip open state -- Ring ground detector Line test: -- Line test modes (ac or dc): 1. Voltage tip to ground 2. Voltage ring to ground 3. Voltage tip to ring 4. Current tip to ring 5. Current tip to ground 6. Current ring to ground -- Inject test tones through codec interface or dedicated input pin -- Analog output at dedicated output pin RFI/EMC-CISP-22 Integrated 2 Form C ring relay: -- Low impulse noise -- Current-limited switches -- Break-before-make and make-before-break switching Meets Telcordia Technologies* GR1089 requirements with external protection device 44-pin, surface-mount plastic package (PLCC)
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Description
The L9311 electronic line interface and line access circuit (LILAC) provides all the functions that are necessary to interface a codec to the tip and ring of a subscriber loop, integrating the battery feed and ringing access relay in one low-power, low-cost package. The physical construction of the device is two chips. The first chip is manufactured in Agere 90 V complementary bipolar integrated circuit (CBIC-S) technology. This chip contains the SLIC functionality:
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ac transmission path dc feedback and functions Active dc current limit Active mode loop supervision Thermal shutdown
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* Telcordia Technologies is a registered trademark of Bell Communications Research, Inc.
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
A low-power scan mode is available to reduce idle mode on-hook power. This mode is realized by using a scan clamp circuit. In low-power scan mode:
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Description (continued)
The second chip is manufactured in Agere dielectrically isolated 320 V bipolar CMOS diffused metal oxide semiconductor (BCDMOS III) technology. This chip contains the following:
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The scan clamp circuitry is active. Loop closure is active. All ac transmission, dc feed, and other supervision circuits, including ring trip, are shut down. Test is powered down. Thermal shutdown is active. Low battery sense shutdown is on. On-hook transmission is disabled.
Ring access relay Scan clamp circuitry
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Logic control
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Ring trip
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Test
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Thermal shutdown Battery monitor circuit
The LILAC family requires a +5 V and battery supply to operate. No -5 V supply is required. A battery switch is included that automatically, based on subscriber loop length, will apply either the primary higher-voltage battery or an optional lower-voltage auxiliary battery. Use of this feature will minimize off-hook power dissipation. The switch point is a function of the user-programmed dc current limit and the magnitude of the auxiliary battery. Switching from the high-voltage to low-voltage battery is quiet, without interruption of the dc loop current, thus preventing any impulse noise generation at the switch point. Design equations for the switch point and a graph showing loop/battery current versus loop resistance are given in the dc Characteristics section of this data sheet. If the user does not want to provide an auxiliary battery, the design of the L9311 battery switch allows use of a power control resistor at the auxiliary battery input. This scheme will not reduce short-loop, off-hook power dissipation, but it will control power dissipation on the SLIC by sharing power among the SLIC, power resistor, and dc loop. However, in most cases, without the auxiliary battery, the power dissipation capabilities of the 44-pin PLCC package are adequate so that the power control resistor will not be needed. Design equations for power control options are given in the dc Characteristics section of this data sheet. The L9311 has two active transmission ready states, forward active and reverse active. Both on-hook and off-hook transmission are provided during the forward and reverse battery modes. Battery reversal is quiet, without breaking the ac path. Rate of battery reversal may be ramped to control switching time via optional external capacitors. Equations relating rate of battery reversal to these optional external capacitors are given in the dc Characteristics, Power Control section of this data sheet.
A forward disconnect mode, where all circuits are turned off and power is denied to the loop, is also provided. During this mode, the NSTAT supervision output will read on-hook. In the ring mode, the line break switches are opened and the power ring access switches are closed. In this mode, the ring trip detector in the SLIC is active and all other detectors and the tip/ring drive amplifiers are turned off to conserve power. Make-before-break or break-before-make switching is achievable during ring cadence or ring trip. Toggling directly into or directly out of the ring mode table will give make-before-break switching. To achieve breakbefore-make switching, go to an intermediate all-off state (use forward disconnect state) before entering the ring mode or before leaving the ring mode. See the Switching Behavior section of this data sheet for more details on switching behavior. Voltage transients or impulse noise associated with ring cadence or ring trip are minimized or eliminated with the L9311, thus possibly eliminating the need for external zero-cross switching circuitry. A tip open switch configuration is also available for ground start applications. A common-mode current detector is included. Both the ring trip and loop closure supervision functions are included. Loop closure threshold is set by applying a voltage source to the LCTH input. The voltage source may be an external voltage source or derived from the SLIC VREF output. A programmable external voltage source may be used to provide software control of the loop closure threshold. Design equations for the loop closure threshold are given in the Supervision section of this data sheet. Hysteresis is included.
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Description (continued)
The ring trip detector requires only a single-pole filter at the input. This will minimize the required number of external components. To help minimize device power dissipation, the ring trip detector is active only during the power ring mode. Ring trip and loop supervision status outputs appear in a common output pin, NSTAT. NSTAT is an unlatched supervision output; thus, an interrupt-based control scheme may be used. The dc current limit is set in the active modes via an applied voltage source. The voltage source may be an external voltage source. The voltage may be derived via a resistor divider network from the VREF SLIC output. A programmable external voltage source may be used to provide software control of the loop closure threshold. Design equations for this feature are given in the dc Characteristics section of this data sheet. Programming range is 10 mA to 45 mA. Overhead is programmable in the active modes via an applied voltage source. The voltage source may be an external voltage source or derived via a resistor divider network from the VREF SLIC output. A programmable external voltage source may be used to provide software control of the overhead voltage. A potential application of this feature is to increase overhead during test access to accommodate higher voltage test signals. The rate of change of the overhead voltage may be controlled by use of a single external capacitor at the CF1 node. If the rate of change is uncontrolled, there may be audible noise associated with this transition. Design equations for this feature are given in the dc Characteristics section of this data sheet. If the overhead is not programmed via a resistor, the device develops a default overhead adequate for a 3.14 dBm overload into 900 . For the default overhead, OVH is connected to ground. The L9311 provides line test capability. In the test mode, a voltage proportional to the ac or dc tip to ground, ring to ground, tip to ring voltage or current, may be presented at the SLIC TESTLEV output. An ac test tone may also be applied to a test input, TESTSIG, or through the codec RCVN/RCVP interface. TESTSIG input is active upon entering a test state and remains active after leaving the test mode. By varying the frequency of the applied test tone, parameters such as line capacitance may be measured.
TESTSIG should be externally connected to the device's VREF if it is not used during a test condition. This may be done by a high-impedance pull-up resistor. Additionally, TESTSIG should be ac coupled to the test signal generator. Test level outputs at TESTLEV are referenced to the internally generated reference voltage VREF. This reference voltage may also be output at TESTLEV so the users can compensate test results at TESTLEV for the internal reference. Note that during nontest modes, TESTLEV is high impedance to conserve power. Input TESTSIG is turned off during any nontest mode and during the VREF test mode. The various test modes are achieved through a series of integrated analog switches that can reconfigure the SLIC to provide normal SLIC operation or the appropriate test function. Details are given in the Special Functions, Line Test section of this data sheet. Test modes are achieved through the device state table. When entering a test mode, the state of the SLIC is unchanged; thus, testing can be done with the SLIC in forward and reverse battery active modes. Additionally, via the line break switches associated with the ring relay, use of a tip open or ring open state is used to make single-ended voltage and current measurements. Data control is via a parallel latched data control scheme. Data latches are edge-level sensitive. Data is latched in when the LATCH control input goes low. While LATCH is low, the user cannot change the data control inputs. The data control inputs may only be changed when LATCH is high. Incorporation of data latches allows for data control information and loop supervision information to be passed to and from the SLIC via data buses rather than on a per-line basis, thus minimizing routing complexity and board routing area. A device RESET pin is included. When this pin is low, the logic inputs are overridden and the device will be reset into SLIC forward disconnect state and the switch into the all-off state. NSTAT is forced to the on-hook condition when RESET is low. The overall device protection is achieved through a combination of an external secondary protector, along with an integrated thermal shutdown feature, a battery voltage window comparator, the break switch foldback characteristic, and the dc/dynamic current-limit response of the break and tip return switches.
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
operating range. During this mode, the NSTAT supervision output will override the actual hook status and force an off-hook or logic low. See the Protection section of this data sheet for more details on device protection. Please contact your Agere Account Representative for a recommended secondary protection device. Longitudinal balance is consistent with North American TR-57 requirements. Transmit and receive gains have been chosen to minimize the number of external components required in the SLIC-codec ac interface, regardless of the choice of codec. The L9311 uses a voltage feed, current sense architecture; thus, the transmit gain is a transconductance. The L9311 transconductance is set via a single external resistor, and this device is designed for optimal performance with a transconductance set at 300 V/A. The L9311 offers an option for a single-ended to differential receive gain of either 8 or 2. These options are mask programmable at the factory and are selected by choice of part number. A receive gain of 8 is more appropriate when choosing a first-generation type codec where termination impedance, hybrid balance, and overall gains are set by external analog filters. The higher gain is typically required for synthesization of complex termination impedance. A receive gain of 2 is more appropriate when choosing a third-generation type codec. Third-generation codecs will synthesize termination impedance, set hybrid balance, and set overall gains. To accomplish these functions, third-generation codecs typically have both analog and digital gain filters. For optimal signal-tonoise performance, it is best to operate the codec at a higher gain level. If the SLIC then provides a high gain, the SLIC output may be saturated causing clipping distortion of the signal at tip and ring. To avoid this situation, with a higher-gain SLIC, external resistor dividers are used. These external components are not necessary with the lower gain offered by the L9311. The RCVP/RCVN SLIC inputs are floating inputs. If there is not feedback from RCVP/RCVN to VITR, RCVP/RCVN may be directly coupled to the codec output. If there is feedback, RCVP/RCVN must be ac-coupled to the codec output. This device is packaged in a 44-pin PLCC surfacemount package.
Description (continued)
For protection against long duration fault conditions, such as power cross and tip/ring shorts, a thermal shutdown mechanism is integrated into the device. Upon reaching the thermal shutdown temperature, the device will enter an all-off mode. Upon cooling, the device will re-enter the state it was in prior to thermal shutdown. Hysteresis is built in to prevent oscillation. During this mode, the NSTAT supervision output overrides the actual loop status and forces an off-hook. The line break switches and tip return switch are current-limited switches. The current-limit mechanism limits current through the switch to the specified dc current limit under low frequency or dc faults (power cross and/or tip/ring to ground short) and limits the current to the specified dynamic current-limit response under transient faults, such as lightning. A foldover characteristic is incorporated into the line break switches within their I-V curve. Under voltage conditions higher than the normal operating range, such as may be seen under an extreme lightning or power cross fault condition, the line break switch will fold over into a low-current state. This feature allows for more relaxed specifications on the ring side protector, thus allowing for higher-voltage ringing signals. (Tip side protector is limited by the requirements on the tip return switch.) This feature is part of the overall device protection scheme. This device uses a window comparator to force an alloff condition if the battery drops below, or rises above, a specified threshold. Upon loss of VBAT1, the L9311 will automatically enter an all-off mode. The device will enter this mode if the magnitude of the battery drops below a nominal 15 V and will remain in this mode until the magnitude of the battery rises above a typical 20 V. During this mode, the NSTAT supervision output will override the actual hook status and force an off-hook or logic low. When the device is in the scan mode, because of the design of the scan clamp circuit, common-mode current can be forced into or out of the battery supply. Because of this, and depending upon power supply design, the magnitude of the battery may rise above the maximum operating condition during extended longitudinal currents or during a power cross fault condition. To prevent excess current from being forced into or out of the battery, if the magnitude of the battery rises typically above 75 V to 80 V, the device will enter an all-off state. The device will remain in the all-off state until the magnitude of the battery drops into the normal
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Architecture
VITR LCF LCTH RESET NSTAT LATCH B3 B2 B1 B0 VPROG VDD DGND +5VD PARALLEL DATA INTERFACE
SWITCHHOOK VREF WINDOW COMPARATOR IN - AAC + FB RB + VTX ITR TRNG SW3 60 PT SW1 18 VITR TESTLEV TEST VREF VTX PR SW2 18 RTS RING TRIP DETECTOR RSW SW4 15 RRING +5VA VBAT RT VBAT VBAT SCAN VBAT BGND SCAN CLAMP BGND ITR BGND ITR/325 RFT VBAT ITR TIP/RING CURRENT SENSE RFR SCAN & RING GND DETECTOR VBAT BGND AX (1 V/50 mA) - 2.35 V BANDGAP REFERENCE VTX 2.35 V VREF CF2 ILC BGND + OUT AT - ac INTERFACE ac IN ILC REF RT CONTROL
TXI
CURRENT LIMITER AND INRUSH CONTROL REF CF2
TESTSIG
RCVP
RCVN FB1 FBRB x1 dc x1 CF1 OVH CF2
+ OUT AR -
FB
FB2
VCC AGND
RGDET
ICM
VBAT2/PWR
VBAT1
VBAT1
BGND
BGND
12-3523d (F)
Figure 1. Architecture Diagram
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Architecture (continued)
VITR
Pin Information
AGND VPROG RCVN RCVP LCTH VITR OVH VREF 2 CF1 CF2 VCC
VTX FB2 VREF + TESTLEV - 66.7 k VDD 5 M PT TEST BLOCK VDD PR 5 M DGND 66.7 k FB1 LCF BGND RPWR VBAT1 VBAT1 BGND TESTSIG TIE A TESTLEV 7 8 9 10 11 12 13 14 15 16
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5
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3
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30
TXI NC ITR VTX ICM RGDET DGND VDD LATCH RESET B0
L9311AP
17 29 18 19 20 21 22 23 24 25 26 27 28 PT NSTAT RTS NC RSW PR B3 B2 RRING TRING B1
DGND
12-3525c (F)
12-3522d (F)
Figure 2. Test Diagram
Figure 3. 44-Pin PLCC
Table 1. Pin Descriptions Pin 1 2 3 Symbol LCTH VREF OVH Type I O I Name/Function Loop Closure Program Input. Connect a voltage source or ground, via a resistor, to this point to program the loop closure threshold. SLIC Internal Reference Voltage. Output of internal 2.35 V SLIC reference voltage. Overhead Voltage Program Input. Connect a voltage source to this point to program the overhead voltage. Voltage source may be external or derived via a resistor divider from VREF. A programmable external voltage source may be used to provide software control of the overhead voltage. If a resistor or voltage source is not connected, the overhead voltage will default to approximately 5.5 V (sufficient to pass 3.14 dBm in to 900 ). If the default overhead is desired, connect this pin to ground. Current-Limit Program Input. Connect a voltage source to this point to program the dc current limit. Voltage source may be external or derived via a resistor divider from VREF. A programmable external voltage source may be used to provide software control of the loop closure threshold. Filter Capacitor. Connect a 0.1 F capacitor from this node to ground for filtering. Filter Capacitor. Connect a capacitor from this node to OVH to control the rate of change of the overhead voltage. If controlled overhead is not desired, leave this node open. Polarity Reversal Slowdown Capacitor. Connect a capacitor from this node to ground to control the rate of battery reversal. If controlled battery reversal is not desired, leave pin is open. Polarity Reversal Slowdown Capacitor. Connect a capacitor from this node to ground to control the rate of battery reversal. If controlled battery reversal is not desired, leave pin is open.
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VPROG
I
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CF2 CF1 FB2
-- -- --
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FB1
--
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Pin Information (continued)
Table 1. Pin Descriptions (continued) Pin 9 Symbol LCF Type -- Name/Function Loop Closure Filter Capacitor. PPM injection can cause false loop closure indication. Connect a capacitor from this node to VCC to filter the loop closure detector. If loop closure filtering is not required, leave this node open. Battery Ground. Ground return for the battery supply. Auxiliary Battery. If a lower-voltage auxiliary battery is used, connect the auxiliary battery supply to this node. If a power control resistor is used, connect the power control resistor from this node to VBAT1. If no power control technique is used, connect this node to VBAT1. Office Battery Supply. Negative high-voltage power supply. Office Battery Supply. Negative high-voltage power supply. Battery Ground. Ground return for the battery supply. Test Input. This input injects a test signal to the line when an appropriate test operational state is chosen. Connect this node to VREF if not used. Connect to VREF. Test Level Output. This output pin will provide a voltage that is proportional to either the dc line voltage, dc line current, ac line voltage, ac line current, or internal reference voltage dependent upon which operational state is selected. No Connect. May not be used as a tie point. Ring Trip Sense. Sense input for the ring trip detector. Ring Lead Ringing Access Switch. Ringing relay connects this pin to pin RRING. Connect this pin to pin PR through a 400 current-limiting resistor. Ringing Access. Input to solid-state ringing access switch. Connect to ringing generator. Protected Ring. The output of the ring driver amplifier and input to loop sensing connected through solid-state break switch. Connect to subscriber loop through overvoltage/ current protection. Protected Tip. The output of the tip driver amplifier and input to loop sensing connected through solid-state break switch. Connect to subscriber loop through overvoltage/current protection. Tip Ringing Return. Ring relay connects this pin to PT. Connect to ringing supply return. Loop Status. The output of the loop status detector (loop start detector wired-OR with ring trip detector). This loop status supervision output is not controlled by the data latch. Data Control Input. See Table 2, Primary Control States and Table 3, Secondary Control States for details. Data Control Input. See Table 2, Primary Control States and Table 3, Secondary Control States for details. Data Control Input. See Table 2, Primary Control States and Table 3, Secondary Control States for details. Data Control Input. See Table 2, Primary Control States and Table 3, Secondary Control States for details. Reset. A logic low will override the B[0:3] and LATCH inputs and reset the state of the SLIC to the disconnect state and the switch to the all-off state. Latch Control Input. Edge-level sensitive control for data latches. 5 V Digital Power Supply. 5 V supply for digital circuitry.
10 11
BGND RPWR
G P
12 13 14 15
VBAT1 VBAT1 BGND TESTSIG
P P G I -- O
16 TIE A' 17 TESTLEV
18 38 19 20 21 22
NC RTS RSW RRING PR
-- I O I I/O
23
PT
I/O
24 25 26 27 28 29 30 31 32
TRING NSTAT B3 B2 B1 B0 RESET LATCH VDD
O O I I I I I I P
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Pin Information (continued)
Table 1. Pin Descriptions (continued) Pin Symbol Type Name/Function 33 DGND G Digital Ground. Ground return for VDD current. 34 RGDET O Ring Ground Detect. When high, this open collector output indicates the presence of a ring ground or a tip ground. This supervision output may be used in ground start, or common-mode fault detection applications. It has an internal pull-up. 35 ICM I Common-Mode Current Sense. To program tip or ring ground sense threshold, connect a resistor to AGND and connect a capacitor to AGND to filter 50 Hz/60 Hz. If unused, the pin is connected to ground. 36 VTX O Tip/Ring Voltage Output. This output is a voltage that is directly proportional to the differential tip/ring current. A resistor from this node to ITR sets the device transimpedance. Gain shaping for termination impedance with a COMBO I codec is also achieved with a network from this node to ITR. 37 ITR I Transmit Gain. A current output which is proportional to the differential current flowing from tip to ring. Input to AX amplifier. Connect a resistor from this node to VTX to set transmit gain to 300 . Gain shaping for termination impedance with a COMBO I codec is also achieved with a network from this node to VTX. 39 TXI I Transmit ac Input (Noninverting). Connect a 0.1 F capacitor from this pin to VTX for dc blocking. 40 VITR O Transmit ac Output Voltage. The output is a voltage that is directly proportional to the differential ac tip/ring current. This output is connected via a proper interface network to the codec. 41 RCVP I Receive ac Signal Input (Noninverting). This high-impedance input controls the ac differential voltage on tip and ring. 42 RCVN I Receive ac Signal Input (Inverting). This high-impedance input controls the ac differential voltage on tip and ring. 43 AGND G Analog Ground. Ground return for VCC current. 44 VCC P 5 V Analog Power Supply. 5 V supply for analog circuitry.
Operating States
Input State Coding
State control is via a tiered logic system. The device must initially be set to a primary control state (B3 = 0). This will set the operational state of the SLIC and switch. The secondary control table (B3 = 1) is used to turn on the PPM amplifier or to turn on the test circuitry and enter a test state. The primary state of the device (the state of the SLIC and switch) will not change when entering a secondary control state. Within the primary control table, each state will set the SLIC and the switch to a specific mode. The exception is the tip-amp and ring-amp states. The tip-amp and ring-amp states will change the configuration of the switches, but leave the state of the SLIC unchanged from the previous primary control mode.
Once a primary (device) control state is selected, the test circuitry can be activated via a secondary control state. Within the secondary control table, there are test active modes. Upon entering a test active mode in the secondary control table, both TESTLEV output and TESTSIG input are active and the test switches set to the appropriate condition. (See Test Architecture Diagram, Figure 2.) An exception is the VREF test active mode. Upon entering VREF, only the TESTLEV output is active, and the internal (2.35 V typical) reference voltage appears at TESTLEV. In the VREF mode, the TESTSIG input is deactivated. Once test is on, the user may reverse the battery, enter the scan, ring, or disconnect modes, in the primary table, without turning off test. Test may also be deactivated by selecting TESToff in the secondary control table.
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Operating States (continued)
Input State Coding (continued)
Data control is via a parallel latched data control scheme. Data latches are edge-level sensitive. Data is latched in when the LATCH control input goes low. Data must be set up 200 ns before LATCH goes low and held 50 ns after LATCH goes high. While LATCH is low, the user should not change the data control inputs at B0, B1, B2, and B3. The data control inputs at B0, B1, B2, and B3 may only be changed when LATCH is high. NSTAT supervision output is not controlled by the LATCH control input. Table 2. Primary Control States B3 0 0 0 0 0 0 0 0 X B2 0 0 0 0 1 1 1 1 X B1 0 0 1 1 0 0 1 1 X B0 0 1 0 1 0 1 0 1 X RESET 1 1 1 1 1 1 1 1 0 State Scan Powerup, forward battery Powerup, reverse battery Tip and ring amp Ring Tip amp Ring amp Disconnect, break before make Disconnect, break before make
Table 3. Secondary Control States B3 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Active TESTLEV, TESTSIG TESTLEV, TESTSIG TESTLEV, TESTSIG TESTLEV, TESTSIG TESTLEV TESTLEV, TESTSIG -- -- Tip/Ring voltage Tip voltage Ring voltage VTX--current VREF VITR--current Unassigned TESToff State
Table 4. Supervision Coding Pin NSTAT 0 = off-hook or ring trip 1 = on-hook and no ring trip Pin TRGDET 0 = ring ground 1 = no ring ground
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
TESTLEV output is in the high-impedance mode, and TESTSIG input is off unless this feature is selected via the secondary control table. NSTAT represents the loop closure detector status.
State Definitions
Primary Control Modes
s
s
Powerup, Forward Battery Scan
s s s
Normal talk and battery feed state. Pin PT is positive with respect to pin PR. All ac transmission and dc feed circuits are powered up. On-hook transmission is enabled. Thermal shutdown is active. Battery window comparator sense shutdown is on. Switch break switches (SW1 and SW2) are closed, and ring access switches (SW3 and SW4) are open. VBAT1 is applied to tip and ring during on-hook conditions. Automatic battery switch selects VBAT1 or VBAT2 during off-hook conditions. All supervision circuits except for ring trip detector are active. TESTLEV output is in the high-impedance mode, and TESTSIG input is off unless this feature is selected via the secondary control table. NSTAT represents the loop closure detector status.
s s s s s s s s s s
Scan clamp circuitry is active. Loop closure is active. All ac transmission, dc feed, and other supervision circuits, including ring trip, are shut down. Thermal shutdown is active. Battery window comparator sense shutdown is on. On-hook transmission is disabled. Pin PT is positive with respect to PR and VBAT1 is applied to tip/ring. Switch break switches (SW1 and SW2) are closed, and ring access switches (SW3 and SW4) are open. NSTAT represents the loop closure detector status.
s s s s
s
s
s
s
s
Ground Start
s s
s
Tip amplifier is on, tip break switch is open. The device presents a high impedance (>100 k) to pin PT and a current-limited battery (VBAT2) to PR. Common-mode current detector is on. Ring trip detector is off. Output RGDET indicates current flowing in the ring lead. This is not a defined state in the primary control mode table. It is achieved via the powerup and the ring amp states in the primary control mode table.
s
Powerup, Reverse Battery
s s s
Normal talk and battery feed state. Pin PR is positive with respect to pin PT. All ac transmission and dc feed circuits are powered up. On-hook transmission is enabled. Thermal shutdown is active. Battery window comparator sense shutdown is on. Switch break switches (SW1 and SW2) are closed, and ring access switches (SW3 and SW4) are open.
s
s s s s
Ringing
s
Switch break switches (SW1 and SW2) are open, and ring access switches (SW3 and SW4) are closed. Tip/ring drive amplifiers are powered down. Ring trip circuit is active. Loop supervision and common-mode current detectors are powered down. NSTAT represents the ring trip detector status.
s s
VBAT1 is applied to tip and ring during on-hook conditions. Automatic battery switch selects VBAT1 or VBAT2 under off-hook conditions. All supervision circuits except for ring trip detector are active.
s s
s
s
s
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
State Definitions (continued)
Primary Control Modes (continued)
Disconnect--Break Before Make
s
Secondary Control Mode States
Voltage: Tip to Ground
s
A voltage proportional to the tip to ground voltage appears at the TESTLEV output. TESTSIG input is on. Customer applies ac test tone or VREF to TESTSIG to select an ac or dc measurement.
The tip and ring amplifiers are turned off to conserve power. Break switches (SW1 and SW2) are open, and ring access switches (SW3 and SW4) are open. This mode is also used as a transitional mode to achieve break-before-make switching from the power ring to active or scan mode. All supervision circuits are powered down; NSTAT overrides the actual loop condition and is forced high (on-hook).
s s
s
Voltage: Ring to Ground
s
s
A voltage proportional to the ring to ground voltage appears at the TESTLEV output. TESTSIG input is on. Customer applies ac test tone or VREF to TESTSIG to select an ac or dc measurement.
s s
Tip Amp
s
Tip side break switch is closed, and ring side break switch and ring access switches are open. SLIC mode is unaffected by reconfiguring the ring relay via this mode; thus, SLIC will remain in the mode it was in prior to selecting this mode.
Voltage: Tip to Ring
s
s
A voltage proportional to the differential tip to ring voltage appears at the TESTLEV output. TESTSIG input is on. Customer applies ac test tone or VREF to TESTSIG to select an ac or dc measurement.
s s
Ring Amp
s
Ring side break switch is closed; tip side break switch and ring access switches are open. SLIC mode is unaffected by reconfiguring the ring relay via this mode; thus, SLIC will remain in the mode it was in prior to selecting this mode.
Current: Tip to Ring--VTX
s
s
A voltage proportional to the ac, plus dc tip to ring differential current, tip to ground current, or ring to ground current appears at the TESTLEV output. Use this state for dc measurements. Choice is determined by primary control mode table. Differential current is selected by choosing powerup forward or reverse from the primary control mode table. Tip to ground or ring to ground current is selected by first choosing powerup forward or reverse from the primary mode table, then choosing tip amp or ring amp from the primary mode table. TESTSIG input is on. Customer applies ac test tone or VREF to select an ac or dc measurement.
Tip and Ring Amp
s s
Tip and ring side break switches are open; ring access switches are open. SLIC mode is unaffected by reconfiguring the break switches via this mode; thus, SLIC will remain in the mode it was in prior to selecting this mode. This is the calibration mode for differential and single-ended tip/ring current measurements.
s
s
s
s
s
Reset
s s
Selection of device reset via the RESET pin will set the device into the disconnect break-before-make state.
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Special States
Thermal Shutdown
s s
State Definitions (continued)
Secondary Control Mode States (continued)
Current: Tip to Ring--VITR
s
Not controlled via truth table inputs. This mode is caused by excessive heating of the device, such as may be encountered in an extended power cross situation. Upon reaching the thermal shutdown temperature, the device will enter an all-off mode. Upon cooling, the device will re-enter the state it was in prior to thermal shutdown. Hysteresis is built in to prevent oscillation. In this mode, supervision output NSTAT is forced low (off-hook) regardless of loop status or if the disconnect logic state is selected.
A voltage proportional to the ac tip to ring differential current, tip to ground current, or ring to ground currents, appears at TESTLEV output. Use this state for ac measurements. Choice is determined by primary control mode table.
s
s s
s
Differential current is selected by choosing powerup forward or reverse from the primary control mode table. Tip to ground or ring to ground current is selected by first choosing powerup forward or reverse from the primary mode table, then choosing tip amp or ring amp from the primary mode table. TESTSIG input is on.
s
s
Battery Out of Range
s
s s
Not controlled via truth table inputs. This mode is caused by a battery out of range; that is, the battery voltage rising above or below a specified threshold. Upon reaching the specified high or low battery voltage, the device will enter an all-off mode. Upon the battery returning to the specified normal operating range, the device will re-enter the state it was in prior to the low battery shutdown. Hysteresis is built in to prevent oscillation. In this mode, supervision output NSTAT is forced low (off-hook) regardless of loop status or if the disconnect logic state is selected.
Customer applies ac test tone or VREF to select an ac or dc measurement.
s
Reference Voltage
s s
A voltage proportional to the internal dc reference voltage VREF appears at the TESTLEV output.
s
s s
TESTSIG input is off. This is the calibration state for voltage measurements.
s
TEST Off
s s s s
Device mode is per primary control mode table. The TESTSIG input is deactivated. TESTLEV output is high impedance. Device mode is per primary control mode table.
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Absolute Maximum Ratings (at TA = 25 C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.
Parameter 5 V dc Supplies (VCC + VDD) High Office Battery Supply (VBAT1) Auxiliary Office Battery Supply (VBAT2) Ringing Voltage Logic Input Voltage Maximum Junction Temperature Storage Temperature Range Relative Humidity Range Switch 1, 2, 3; Pole to Pole Switch 4; Pole to Pole Switch Input to Output
Symbol -- -- -- -- -- -- -- -- -- -- --
Min -0.5 -75 -- -- -0.5 -- -40 5 -- -- --
Max 7.0 0.5 VBAT1 to 0.5 V 110 VCC + 0.5 V 165 125 95 320 465 320
Unit V V V Vrms V C C % V V V
Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. For example, inductance in a supply lead could resonate with the supply filter capacitor to cause a destructive overvoltage.
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Electrical Characteristics
In general, minimum and maximum values are testing requirements. However, some parameters may not be tested in production because they are guaranteed by design and device characterization. Typical values reflect the design center or nominal value of the parameter; they are for information only and are not a requirement. Minimum and maximum values apply across the entire temperature range (-40 C to +85 C) and entire battery range (-36 V to -70 V). Unless otherwise specified, typical is defined as 25 C, VCC = VDD = 5.0, VBAT1 = -48 V VBAT2 = -25 V. Positive currents flow into the device. Table 5. Device Operating Conditions and Powering Parameter Temperature Range Humidity Range VBAT1 Operational Range VBAT2 Operational Range 5 V dc Supplies (VCC, VDD) Supply Currents, Scan State No Loop Current, VBAT = -48 V, VCC = VDD = 5 V: IVCC+VDD IVBAT1 Power Dissipation Supply Currents, Forward/Reverse Active No Loop Current, with On-hook Transmission, Test Not Active, VBAT = -48 V, VCC = VDD = 5 V: IVCC+VDD IVBAT1 Power Dissipation Supply Currents, Forward Disconnect, VBAT = -48 V, VCC = VDD = 5 V: IVCC+VDD IVBAT1 Power Dissipation Supply Currents, Ring State, No Loop Current, VBAT = -48 V, VCC = VDD = 5 V, VRING = 80 Vrms: IVCC+VDD IVBAT1 IRING Generator Power Dissipation Power Adders, VCC = VDD = 5 V, Power for Test Amplifiers Drawn Only from 5 V Supply: Test PSRR 500 Hz--3000 Hz: VBAT1, VBAT2 VCC Thermal Protection Shutdown (TTSD)
* Not to exceed 26 grams of water per kilogram of dry air.
Min -40 5 -36 -19 4.75
Typ -- -- -48 -25 5.0
Max 85 95* -72 VBAT1 5.25
Unit C %RH V V V
-- -- --
2 100 15
2.5 200 22
mA A mW
-- -- -- -- -- --
6 1.1 83 1.2 65 9
6.5 1.4 100 1.85 275 22.5
mA mA mW mA A mW
-- -- -- --
4 200 500 70
-- -- -- --
mA A A mW
-- 45 30 150
5 -- -- 165
-- -- -- --
mW dB dB C
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Electrical Characteristics (continued)
Ring Trip Detector
Table 6. Ring Trip Detector Parameter Voltage at Input that will Cause Ring Trip After Appropriate Zero Crossings Voltage at Input that will Cause Immediate Ring Trip Ringing Source : Frequency (f) dc Voltage ac Voltage Ring Trip (NDET = 0)2, 3: Loop Resistance Trip Time NDET Valid
1
Min 2.5 12 19 -39.5 60 2000 -- --
Typ 3 15 20 -- -- -- -- --
Max 3.5 18 28 -57 105 -- 200 80
Unit V V Hz V Vrms ms ms
1. The ringing source may be either of the following: a.) The ringing source consists of the ac and dc voltages added together (battery-backed ringing); the ringing return is ground. b.) The ringing source consists of only the ac voltage (earth-backed ringing); the ringing return is the dc voltage. 2. NDET must also indicate ring trip when the ac ringing voltage is absent (<5 Vrms) from the ringing source. 3. Pretrip ringing must not be tripped by a 10 k resistor in parallel with an 8 F capacitor applied across tip and ring.
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Electrical Characteristics (continued)
Test
Table 7. ac Test Source Parameter Test Frequency (f1) Signal Gain (TESTSIG to amplifier outputs) VTESTSIG = 0.35 V Signal Gain Voltage Coefficient Input Signal Harmonic Distortion3 Source1, 2: Min -- -- -- 0 -- Typ -- 10 1.27 -- -- Max 100 -- -- 1.25 5 Unit kHz -- 1/V Vrms %
1. ac test signal should be ac coupled into TESTSIG. 2. A pull-down resistor to VREF should be connected to TESTSIG. 3. This parameter is not tested in production, it is guaranteed by design and characterization.
Table 8. Test Sense Parameter Single-ended Voltage Gain 10 V on Tip/Ring Differential Voltage Gain 10 V on Tip/Ring Voltage Gain Accuracy (single-ended or differential) Voltage Coefficient Current Gain at VTX (dc) Differential Current Gain at VTX (dc) Single-ended Current Gain at VITR (ac) Differential Current Gain at VITR (ac) Single-ended Overload at VTX2 Overload at VREF VREF Accuracy TESTLEV Offset Relative to VREF TESTLEV Amplifier Output Voltage Swing Input Voltage Swing VITR 2 Min -- -- -3.5 -- 19.6 9.8 291 145.5 105 7 -- -5 -40 AGND + 0.35 AGND + 0.35 Typ 1/75 1/75 -- 0.011 20 10 300 150 -- -- 2.35 -- -- -- -- Max -- -- 3.5 -- 20.4 10.2 309 154.5 -- -- -- 5 40 VCC - 0.4 VCC - 1.0 Unit -- -- % %/V V/A V/A V/A V/A mA mA V % mV V V
1. This is the voltage coefficient with respect to tip/ring voltage. See Table 20 TESTLEV Output Options (Tip-to-Ring, Tip-to-Ground, and Ringto-Ground equations) for application of this parameter. 2. This parameter is not tested in production, it is guaranteed by design and characterization.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Electrical Characteristics (continued)
SLIC Two-Wire Port
Table 9. SLIC Two-Wire Port Parameter PT and PR Drive Current = dc + Longitudinal + Signal Currents Signal Current Longitudinal Current Capability per Wire (longitudinal current is independent of dc loop current) dc Active Mode Loop Current - ILIM (RLOOP = 100 ): Programming Range Voltage at VPROG dc Current-limit Variation: VPROG = 0.8 V (ILIMIT = 40 mA) Loop Resistance Range (from PT/PR) (3.17 dBm overload into 600 ): ILOOP = 20 mA at VBAT1 = -48 V VREF Offset at VPROG dc Feed Resistance (includes internal SLIC dc resistance and break switch resistance) dV/dT Sensitivity at PT/PR Ground Start State PT Resistance Powerup Open Loop Voltages (VBAT1 = -48 V): Forward/Reverse Active Mode |PT - PR| - VBAT1 Voltage at OVH Forward/Reverse Active Mode |PT - PR| - VBAT1, VOVH = 0 Common Mode Powerup Open Loop Voltages: Scan Mode |PT - PR| - VBAT1 Loop Closure Threshold: Voltage at LCTH Loop Closure Threshold Hysteresis Ground Start: Gain ICM to RGDET Common-mode Detector Threshold Longitudinal to Metallic Balance at PT/PR (IEEE* Std. 455): 200 Hz to 3.4 kHz Metallic to Longitudinal (harm) Balance: 200 Hz to 4000 Hz
* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Min 105 10 8.5
Typ -- -- 15
Max -- -- --
Unit mApeak mArms mArms
10 0.2 -- 1900 2.23 -40 50 -- 100 5.5 0 5.5 -- 0 0 -- -- 5 61 40
-- -- 5 -- 2.35 -- 75 200 -- -- -- 6.1 (VBAT1 + 1)/2 -- -- 20 1 -- -- --
45 0.9 -- -- 2.47 40 110 -- -- 15 1.9 -- -- 13.5 VREF -- -- 10 -- --
mA V % V mV V/s k V V V V V V % A/mA mA dB dB
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Electrical Characteristics (continued)
Analog Pin Characteristics
Table 10. Analog Pin Characteristics Parameter TXI (input impedance) VPROG Input Bias Current* (current flow out of pin) LCTH Input Bias Current* (+ current flows into pin) VTX: Output Offset Output Drive Current Output Voltage Swing (1 mA load): Maximum Minimum Output Short-circuit Current Output Load Resistance* Output Load Capacitance* VITR: Output Offset Output Drive Current Output Voltage Swing (1 mA load): Maximum Minimum Output Short-circuit Current Output Load Resistance* Output Load Capacitance* RCVN and RCVP: Input Voltage Range (VCC = 5.0 V) Input Bias Current Min 75 -- -- -- 1 AGND AGND + 0.35 -- 10 -- -- 1 AGND AGND + 0.35 -- 10 -- 0 -- Typ 105 -50 50 -- -- -- -- -- -- 50 -- -- -- -- -- -- 50 -- -- Max -- -250 250 40 -- VCC VCC - 0.4 50 -- -- 100 -- VCC VCC - 0.4 50 -- -- VCC - 0.5 1.5 Unit k nA nA mV mA V V mA k pF mV mA V V mA k pF V A
* This parameter is not tested in production. It is guaranteed by design and device characterization.
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Electrical Characteristics (continued)
ac Feed Characteristics
Table 11. ac Feed Characteristics Parameter ac Termination Impedance Total Harmonic Distortion (200 Hz--4 kHz) 2: Off-hook On-hook Transmit Gain3 f = 1004 Hz, 1020 Hz: PT/PR Current to VITR Receive Gain, f = 1004 Hz, 1020 Hz Open Loop: RCVP or RCVN to PT--PR (gain = 8) RCVP or RCVN to PT--PR (gain = 2) ac Feed Resistance (includes internal SLIC ac resistance and break switch resistance) Gain vs. Frequency (transmit and receive)2 900 = 2.16 F Termination, 1004 Hz Reference: 200 Hz--300 Hz 300 Hz--3.4 kHz 3.4 kHz--20 kHz 20 kHz--266 kHz Gain vs. Level (transmit and receive)2 0 dBV Reference: -55 dB to +3.0 dB Idle-channel Noise (tip/ring) 600 Termination: Psophometric C-Message 3 kHz Flat Idle-channel Noise (VTX) 600 Termination: Psophometric C-Message 3 kHz Flat
1
Min 150 -- -- -291 7.76 1.94 50
Typ 600 -- -- -300 8 2 75
Max 1400 0.3 1.0 -309 8.24 2.06 110
Unit % % V/A -- --
-0.3 -0.05 -3.0 -- -0.05 -- -- -- -- -- --
0 0 0 -- 0 -82 8 -- -82 8 --
0.05 0.05 0.05 2.0 0.05 -77 13 20 -77 13 20
dB dB dB dB dB dBmp dBrnC dBrn dBmp dBrnC dBrn
1. Set externally either by discrete external components or a third- or fourth-generation codec. Any complex impedance R1 + R2 || C between 150 and 1400 can be synthesized. 2. This parameter is not tested in production. It is guaranteed by design and device characterization. 3. VITR transconductance depends on the resistor from ITR to VTX. This gain assumes an ideal 6.34 k, the recommended value. Positive current is defined as the differential current flowing from PT to PR.
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Electrical Characteristics (continued)
Logic Inputs and Outputs, VDD = 5.0 V
Table 12. Logic Inputs and Outputs Parameter Input Voltages: Low Level High Level Input Current: Low Level (VDD = 5.25 V, VI = 0.4 V) High Level (VDD = 5.25 V, VI = 2.4 V) Output Voltages (CMOS): Low Level (VDD = 4.75 V, IOL = 180 A) High Level (VDD = 4.75 V, IOH = -20 A) Symbol VIL VIH IIL IIH VOL VOH Min -0.5 2.0 -- -- 0 2.4 Typ 0.4 2.4 -- -- 0.2 -- Max 0.7 VDD 50 50 0.4 VDD Unit V V A A V V
Timing Requirements
Table 13. Timing Requirements Parameter Minimum Setup Time from B0, B1, B2, B3 to LATCH Minimum Hold Time from LATCH to B0, B1, B2, B3 Symbol tSU tHL Min 200 50 Typ -- -- Max -- -- Unit ns ns
Data control is via a parallel latched data control scheme. Data latches are edge-level sensitive. Data is latched in when the LATCH control input goes low. Data must be set up tSU ns before LATCH goes low and held tHL ns after LATCH goes high. While LATCH is low, the user should not change the data control inputs at B0, B1, B2, and B3. The data control inputs at B0, B1, B2, and B3 may only be changed when LATCH is high. NSTAT supervision output is not controlled by the LATCH control input.
LATCH tSU B0, B1, B2, B3
12-3526(F)
tHL
Figure 4. Timing Requirements
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Electrical Characteristics (continued)
Switch Characteristics
Table 14. Break Switches (SW1, 2) Parameter Off State: Maximum Differential Voltage dc Leakage Current (Vsw = 320 V) On State (see On-State I-V Switch Characteristics section): Resistance Maximum Differential Voltage (VMAX)2 Foldback Voltage Breakpoint 1 (V1) Foldback Voltage Breakpoint 2 (V2) dc Current Limit 1 (ILIMIT1) dc Current Limit 2 (ILIMIT2) Dynamic Current Limit 10 x 700 s, 1000 V Applied Surge T < 0.5 s dV/dT Sensitivity2, 3 Min -- -- -- -- 72 V1 + 0.5 105 2 -- -- Typ -- -- 18 -- -- -- 250 -- 2.5 200 Max 3201 20 28 320 -- -- 450 -- -- -- Unit V A V V V mA mA A V/s
1. At 25 C, maximum voltage rating has a temperature coefficient of 0.167 V/C. 2. This parameter is not tested in production. It is guaranteed by design and device characterization. 3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dT sensitivity.
Table 15. Ring Return Switch (SW3) Parameter Off State: Maximum Differential Voltage dc Leakage Current (Vsw = 320 V) On State (see On-State Switch I-V Characteristics section): Resistance Maximum Differential Voltage (VMAX)2 dc Current Limit Dynamic Current Limit 10 x 700 s, 1000 V Applied Surge T = 0.5 s dV/dT Sensitivity2, 3 Min -- -- -- -- -- -- -- Typ -- -- 60 -- 200 2.5 200 Max 3201 20 100 130 -- -- -- Unit V A V mA A V/s
1. At 25 C, maximum voltage rating has a temperature coefficient of 0.167 V/C. 2. This parameter is not tested in production. It is guaranteed by design and device characterization. 3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dT sensitivity.
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Electrical Characteristics (continued)
Switch Characteristics (continued)
Table 16. Ringing Access Switch (SW4) Parameter Off State: Maximum Differential Voltage dc Leakage Current (Vsw = 475 V) (pole to pole) Isolation On State (see On-State Switch I-V Characteristics section): Resistance Voltage Steady-state Current1 Surge Current (10 x 700 s pulse)2 Release Current dV/dT Sensitivity2, 3 Min -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- 500 200 Max 475 20 320 15 3 150 2 -- -- Unit V A V V mA A A V/s
1. Choice of secondary protector and feed resistor should ensure these ratings are not exceeded. A minimum 400 feed resistor is recommended. 2. This parameter is not tested in production. It is guaranteed by design and device characterization. 3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dT sensitivity.
On-State Switch I-V Characteristics
ISW ILIM1 2/3 RON -VMAX -V2 -V1 -ILIM2 -1.5 RON +1.5 ILIM2 VSW +V1 +V2 +VMAX
ISW +ILIMIT
CURRENT LIMITING
ISW
RON 2/3 RON -VMAX RON -1.5 V +1.5 V +VMAX VSW -VOS +VOS VSW
-ILIM1 2/3 RON RON -ILIMIT CURRENT LIMITING
5-5990.c(F)
12-3291.a(F)
12-3292.a(F)
A. Line Break Switch SW1, SW2
B. Ring Return SW3
C. Ring Access SW4
Figure 5. On-State Switch I-V Characteristics
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Test Configurations
TESTSIG TRING RING RSW RTS RING RLOOP TIP OVH VPROG LCTH VREF 0.1 F VCC FB1 FB2 CF1 0.1 F LCF RESET FB1 LATCH FB2 B3 CF1 B2 CF2 B1 B0 50 100 /600 50 PT OVH VPROG LCTH VREF TRING RRING RCVP RSW RTS PR RCVN VITR 0.1 F 4.13 k (GAIN = 2) 46.4 k (GAIN = 8) TESTLEV 20 k
TESTSIG TESTLEV
RCV 20 k
VREF VITR
L9311 BASIC TEST CIRCUIT
TXI VTX 6.34 k ITR
RESET LATCH B3 B2 B1 B0
PWR/ VBAT2
VBAT1 BGND VCC
AGND
VDD
DGND
ICM RGDET NSTAT
0.1 F 0.1 F VBAT2/PWR VBAT1
0.1 F
0.1 F 1000 pF 235 k RGDET NSTAT
VCC
VDD
12-3524E (F)
Figure 6. Basic Test Circuit
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Test Configurations (continued)
100 F
VBAT OR VCC 100 VS 4.7 F DISCONNECT BYPASS CAPACITOR
PT VS 368 368
+
VM BASIC TEST CIRCUIT PR
-
100 F
VBAT OR VCC
LONGITUDINAL BALANCE = 20 log
PT
VS VM
+
900 VT/R BASIC TEST CIRCUIT PR
ANSI*/IEEE STANDARD 455-1985
12-2584 (F)
-
Figure 9. Longitudinal Balance
ILONG
VS PSRR = 20 log --------VT/R
12-2582 (F)
PT
+
VPT
-
Figure 7. Metallic PSRR
-
ILONG VBAT OR VCC 100 VS 4.7 F VPR
BASIC TEST CIRCUIT
+
PR
DISCONNECT BYPASS CAPACITOR
ZLONG =
VPR VPT OR ILONG ILONG
12-2585 (F)
Figure 10. Longitudinal Impedance
VBAT OR VCC 67.5 PT 10 F BASIC TEST CIRCUIT
PT
VITR
VITR
+
VM
67.5 PR 56.3 10 F
+
600 VT/R BASIC TEST CIRCUIT PR RCV RCV VS
12-2583 (F)
-
-
VS PSRR = 20 log -----VM
Figure 8. Longitudinal PSRR
GXMT = GRCV =
VITR VT/R VT/R VRCV
12-2587.i (F)
* ANSI is a registered trademark of the American National Standards Institute, Inc.
Figure 11. ac Gains 27
Agere Systems Inc.
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Applications
dc Characteristics
Power Control Under normal device operating conditions, thermal design must ensure that the device temperature does not rise above the thermal shutdown. Power dissipation is highest with higher battery voltages, with higher current limit, and under shorter dc loop conditions. Higher ambient temperature will reduce thermal margin. Power control may be done in several ways, by use of the integrated automatic battery switch and a lowervoltage auxiliary battery or by use of a power control resistor with single battery operation. The thermal capability of the 44-pin PLCC package is sufficient to allow for single battery operation without the power control resistor when the device is used under lowerpower operating conditions. Power Derating Operating temperature range, maximum current limit, maximum battery voltage, minimum dc loop length, and protection resistors' values, number of PCB board layers, and airflow, will influence the overall thermal performance. The still-air thermal resistance of the 44-pin PLCC package is typically 38 C/W for a two-layer board with 0 LFPM airflow. The L9311 will enter thermal shutdown at a temperature of 150 C. The thermal design should ensure that the SLIC does not reach this temperature under normal operating conditions. For this example, assume a maximum ambient operating temperature of 85 C, a maximum current limit of 30 mA, and a maximum battery of -56 V. Further assume a (worst-case) minimum dc loop of 20 for wire resistance, 50 protection resistors, and 200 for the handset. Include the effects of parameter tolerance in these calculations. TTSD - TAMBIENT(max) = allowed thermal rise 150 C - 85 C = 65 C Allowed thermal rise = package thermal impedance x SLIC power dissipation 65 C = 38 C/W x SLIC power dissipation Allowed SLIC power dissipation (PD) = 1.71 W
Thus, in this example, if the total power dissipated on the SLIC is less than 1.71 W, it will not enter thermal shutdown. Total SLIC power is calculated: Total PD = maximum battery x (maximum current limit) (current limit accuracy) + SLIC quiescent power. For the L9311, the worst-case SLIC on-hook active quiescent power is 100 mW. Thus, Total off-hook power = (ILOOP)(1.05) x (VBATAPPLIED) + SLIC quiescent power Total off-hook power = (0.030 A)(1.05) x (52) + 100 mW Total off-hook power = 1.864 W The power dissipated in the SLIC is the total power dissipation less the power that is dissipated in the loop. SLIC PD = total power - loop power Loop off-hook power = (ILOOP x 1.05)2 x (RLOOPdcmin + 2RP + RHANDSET) Loop off-hook power = {(0.030 A)(1.05)}2 x (20 + 100 + 200 ) Loop off-hook power = 317.5 mW SLIC off-hook power = total off-hook power - loop offhook power SLIC off-hook power = 1.864 W - 0.3175 W SLIC off-hook power = 1.5465 W < 1.71 W Thus, under the operating conditions of this example, the thermal capability of the 44-pin PLCC package is adequate to ensure that the L9311 will not be driven into thermal shutdown and no additional power control measures are needed. If, however, for a given set of operating conditions, the thermal capabilities of the package are not adequate to ensure the SLIC is driven into thermal shutdown, then one of the power control techniques described below should be used. Additionally, even if the thermal capability of the 44-pin PLCC package is adequate to ensure that the L9311 will not be driven into thermal shutdown, the battery switch technique described below can be used to reduce total short-loop power dissipation.
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Note that to minimize power statistically, this may not be the best choice for VBAT2. Over a large number of lines, power is minimized according to the statistical distribution of loop resistance.
Applications (continued)
dc Characteristics (continued)
Automatic Battery Switch Use of the automatic battery switch controls power dissipation by automatically switching to the lower-voltage auxiliary battery under short dc loop conditions, thus reducing the short-loop power that is generated. This has the advantage of not only controlling device temperature rise, but reducing overall power dissipation. The switch will automatically apply the appropriate battery to support the dc loop. No logic control is needed to control the switch. Switching is quiet, and the dc loop current will not be interrupted when switching between batteries. The lower-voltage auxiliary battery is connected to the VBAT2/PRW package pin. The equation governing the switch point is as follows: VBAT2 - 3.0 RLOOP = ----------------------------------- - 2RP - Rdc ILIM A graph showing loop and battery current versus loop resistance with use of the battery switch is shown in Figure 12. The VBAT2 voltage must be chosen properly so that the power dissipation is minimized. When the voltage at pin PR equals VBAT2 + 1 V + (50 x ILOOP), at least 98% of the loop current minus 2.5 mA flows into VBAT2 and 2.5 mA + 2% of the loop current plus quiescent current flows into VBAT1. To choose VBAT2, add: 1. Maximum tip overhead voltage (2 V for VOVH = 0). 2. Maximum loop voltage (maximum loop resistance, protection resistance, and dc feed resistance [100 ] times the maximum loop current limit). 3. 1 V for the soft switch. Thus, for a 40 mA current limit, 640 loop, 30 protection resistors, and 3.17 dBm signal (VOVH = 0): VBAT2 = -(2 + 0.042 x (100 + 60 + 640) + 1) = -36.6 V Then, for any loop resistance from 0 to 640 , the worst-case VBAT1 and VBAT2 currents will be: IBAT1 = 1.39 mA + 2.5 mA + 0.02 x (42 mA - 2.5 mA) = 4.68 mA IBAT2 = (0.98) x 42 mA = 38.71 mA Total max power = 1.641 W (VBAT = -48 V)
0.030 ILOOPdc 0.028 0.026 0.024 BATTERY/LOOP CURRENT (mA) 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.002 0.000 0 200 400 600 800 1000
12-3470a (F)
IBAT1
IBAT2
RLOOP ()
Figure 12. L9311 Loop/Battery Current (with Battery Switch) vs. Loop Resistance Power Control Resistor Device temperature rise may be controlled with use of a single battery voltage by use of a power control resistor. This technique will reduce power dissipation on the chip, by sharing the total power not dissipated in the loop between the L9311 and the power control resistor. It does not, however, reduce the total power consumed, as does use of the auxiliary battery. The power control resistor is connected from the primary battery to the VBAT2/PWR node of the device.
Agere Systems Inc.
29
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Applications (continued)
dc Characteristics (continued)
Power Control Resistor (continued) The magnitude of the power control resistor must be low enough to ensure that sufficient power is dissipated on the resistor to ensure the L9311 does not exceed its thermal shutdown temperature. At the same time, the more power that is dissipated by the power control resistor, the higher the resistor's power rating must be, and thus, the more costly the resistor. The following equations are used to optimize the choice (magnitude and power rating) of the power control resistor. Again assume: TTSD - TAMBIENT(max) = allowed thermal rise 150 C - 85 C = 65 C Allowed thermal rise = package thermal impedance x SLIC power dissipation 65 C = 38 C/W x SLIC power dissipation Allowed SLIC power dissipation (PD) = 1.71 W This time, assume a maximum ambient operating temperature of 85 C, a maximum current limit of 45 mA (including tolerance), and a maximum battery of -56 V. Again, assume a (worst-case) minimum dc loop of 0 and that 50 protection resistors are used. Assume the handset is 200 : Total PD = (56 V x 45 mA) + 0.100 W Total PD = 2.34 W + 0.100 W Total PD = 2.4375 W Again, the power dissipated in the SLIC is the total power dissipation less the power that is dissipated in the loop. SLIC PD = total power - loop power Loop power = (ILIM)2 x (RLOOPdcmin + 2RP + RHANDSET) Loop power = (45 mA)2 x (0 + 100 + 200 ) Loop power = 0.6075 W SLIC power = 2.4375 W - 0.6075 W SLIC power = 1.83 W > 1.5 W Under these extreme conditions, thermal margin is increased via an external power control resistor. The power dissipated in the power control resistor is calculated by:
where in this example:
PPRW is power in the resistor
VBAT = -52 V VLOOP = ILIM * (RLOOP + RPROT) VROH is the ring-side overhead voltage of the SLIC. Since this device is dc unbalanced, the tip side overhead will remain typically at -2 V and the ring side overhead will vary with the voltage at VOH. For the total tip/ ring default overhead of 5.5 V, the ring overhead is typically 3.5 V. Overhead Voltage Overhead is programmable in the active mode via an applied voltage source at the device's OVH control input. The voltage source may be an external voltage source or derived via a resistor divider network from the VREF SLIC output or an external voltage source. A programmable external voltage source may be used to provide software control of the overhead voltage. The overhead voltage (VOH) is related to the OVH voltage by: VOH = 5.5 V + 5 x VOVH (V) Overall accuracy is determined by the accuracy of the voltage source and the accuracy of any external resistor divider network used and voltage offsets due to the specified input bias current. If a resistor divider from VREF is used, lower magnitude resistor will give a more accurate result due to a lower offset associated with the input bias current; however, lower value resistors will also draw more power from VREF. The sum of programming resistors should be between 75 k and 200 k. Note that a default overhead voltage of 5.5 V is achieved by shorting input pin OVH to analog ground. Internally, the SLIC needs typically 2 V from each supply rail to bias the amplifier circuitry. This can be thought of as an internal saturation voltage. The default overhead provides sufficient headroom for on-hook transmission of a 3.14 dBm signal into 900 . V 3.14 = 10 log -------0.9 V = 1.36 V, which is required over and above the internal saturation voltage for signal swing. 1.36 V + 4 V = 5.36 V < 5.5 V default overhead; thus, a 3.14 dBm into 900 signal is passed without clipping distortion. The overhead voltage accuracy achieved will not only be affected by the accuracy of the internal SLIC circuitry, but also by the accuracy of the voltage source and the accuracy of any external resistor divider network used. Agere Systems Inc.
2
PPRW =
( VBAT - VROH - VLOOP ) 2 ---------------------------------------------------------------------RPWR
30
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
The previous equation describes the active mode steady-state current-limit response. There will be a transient response of the current-limit circuit (with the device in the active mode) upon an on- to off-hook transition. Typical active mode transient current-limit response is given in Table 17. Table 17. Typical Active Mode On- to Off-Hook Tip/ Ring Current-Limit Transient Response Parameter dc Loop Current: Active Mode RLOOP = 100 On- to Off-hook Transition t < 5 ms dc Loop Current: Active Mode RLOOP = 100 On- to Off-hook Transition t < 50 ms dc Loop Current: Active Mode RLOOP = 100 On- to Off-hook Transition t < 300 ms Value ILIM + 60 Unit mA
Applications (continued)
dc Characteristics (continued)
Overhead Voltage (continued) In the scan mode, overhead is unaffected by VOVH and internally fixed by the scan clamp circuitry to within the specified limits. The TESTSIG and RCV inputs will not overload with an input signal swing between ground and VCC - 0.5 V. However, the SLIC output saturation point (at PT/PR) is a function of the device overhead. Default overhead with OVH = 0 is 3.14 dBm into 900 . After that, output signal swing increases 1 V for every volt that overhead is increased. Overhead voltage may need to be increased to accommodate on-hook transmission of higher-voltage signals. The overhead is set with respect to battery voltage and during a test mode, the battery voltage is unknown. With zero voltage on RCV input, the output is battery voltage minus the overhead on the input, which is the main offset. The small RCV input offset that is multiplied by RCV gain to tip/ring output is inconsequential. dc Loop Current Limit In the active modes, dc current limit is programmable via an applied voltage source at the device's VPROG control input. The voltage source may be an external voltage source or derived via a resistor divider network from the VREF SLIC output or an external voltage source. A programmable external voltage source may be used to provide software control of the loop current limit. The loop current limit (ILIM) is related to the VPROG voltage by: ILIM (mA) = 50 x VPROG (V) Note that the overall current-limit accuracy achieved will not only be affected by the specified accuracy of the internal SLIC current-limit circuit (accuracy associated with the 50 term), but also by the accuracy of the voltage source and the accuracy of any external resistor divider network used and voltage offsets due to the specified input bias current. If a resistor divider from VREF is used, a lower magnitude resistor will give a more accurate result due to a lower offset associated with the input bias current; however, lower value resistors will also draw more power from VREF. The sum of the two resistors in the resistor divider should be between 75 k and 200 k. Offset at VPROG and VREF accuracies are specified in Table 8 and Table 9.
ILIM + 20
mA
ILIM
mA
The current limit with the SLIC set in an active mode will be different from the current limit with the SLIC set in the scan mode. This is due to differences in the scan clamp circuit versus the active tip/ring drive amplifiers. The scan mode current limit is fixed and is a function of the internal design of the scan clamp circuit. The steady-state scan mode current limit will be a typical 40 mA to 50 mA and may, over temperature and process, vary typically from 30 mA to 110 mA. The scan clamp current limit will typically settle to its steady-state value within 300 ms. Loop Range The dc loop range is calculated using:
RL =
VBAT - VOH ---------------------------------ILOOP
- 2RP - Rdc
VBAT1 is used because we are calculating the maximum loop range. The loop resistance value where the device automatically switches to VBAT2 is calculated in the Automatic Battery Switch section of this data sheet.
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Applications (continued)
dc Characteristics (continued)
Battery Feed The L9311 operates in a dc unbalanced mode. In the forward active state, under open circuit (on-hook) conditions, with the default overhead chosen, the tip to ring voltage will be a nominal 5.5 V less than the battery. This is the overhead voltage. The tip and ring overhead is achieved by biasing ring a nominal 3.5 V above battery and by biasing tip a nominal 2.0 V below ground. During off-hook conditions, some dc resistance will be applied to the subscriber loop as a function of the physical loop length, protection, and telephone handset. As the dc resistance decreases from infinity (on-hook) to some finite value (off-hook), the tip to ring voltage will decrease as shown in Figure 13.
The dc feed characteristic can be described by:
VBAT - VOH ILOOP = -----------------------------------------------------RLOOP + 2RP + Rdc ( VBAT - VOH ) * RLOOP VT/R = --------------------------------------------------------------RLOOP + 2RP + Rdc
where: ILOOP = dc loop current. VT/R = dc loop voltage. VBAT = battery voltage magnitude. VOH = overhead voltage. RLOOP = loop resistance, including wire and handset resistance. RP = protection resistance. Rdc = SLIC internal dc feed resistance.
50 1 10 k LOOP CURRENT (mA) 40
VTIP TO GND (1/2)Rdc
30 1 Rdc 20
BEGIN CURRENT LIMITING (1/2)Rdc + RLIM (1/2)Rdc VRING TO GND VBAT DECREASING LOOP LENGTH
10
0 0 5 10 15 20 25 30 35 40 45
LOOP VOLTAGE (V)
12-3431a (F) 12-3050.g (F)
Figure 13. Tip/Ring Voltage
Notes: VBAT1 = -48 V. VBAT2 = -24 V.
As illustrated in Figure 13, as loop length decreases, the tip to ground voltage will decrease with a slope corresponding to one-half the internal dc feed resistance of the SLIC (typical 75 ). The ring to ground voltage will also decrease with a slope corresponding to onehalf the internal dc feed resistance of the SLIC, until the SLIC reaches the current-limit region of operation. At that point, the slope of the ring to ground voltage will increase to the sum of one half the internal dc feed resistance plus approximately 10 k.
ILIM = 40 mA (RPROG = 66.5 k).
Figure 14. L9311 Loop Current vs. Loop Voltage
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Longitudinal to Metallic Balance Longitudinal to metallic balance at PT/PR is specified in the Electrical Characteristics section of this data sheet.
Applications (continued)
dc Characteristics (continued)
Battery Feed (continued) Refer to Figure 13 and Figure 14 in this section and to Figure 12 in the Automatic Battery Switch section. Starting from the on-hook condition and going through to a short circuit, the curve passes through two regions: Region 1: on-hook and low loop currents: the slope corresponds to the dc feed resistance of the SLIC (plus any series resistance). The open-circuit voltage is the battery voltage less the overhead voltage of the device. Region 2: current limit: The dc current is limited to a value determined by VPROG. This region of the dc template has a high resistance (10 k). Notice that the I-V curve is uninterrupted when the power is shifted from the high-voltage battery to the low-voltage battery (if auxiliary battery option is used). This is shown in Figure 12 in the Automatic Battery Switch section. Battery Reversal Rate The rate of battery reverse is controlled or ramped by capacitors FB1 and FB2. A chart showing FB1 and FB2 values versus typical ramp time is given below. Leave FB1 and FB2 open if it is not desired to ramp the rate of battery reversal. Table 18. FB1 and FB2 Values vs. Typical Ramp Time CFB1 and CFB2* 0.01 F 0.1 F 0.22 F 0.47 F 1.0 F 1.22 F 1.3 F 1.4 F 1.6 F Transition Time 20 ms 220 ms 440 ms 900 ms 1.8 s 2.25 s 2.5 s 2.7 s 3.2 s
Supervision
Loop Closure
Loop closure supervision threshold is programmed via an applied voltage source or ground, through a resistor at the LCTH input. Loop closure status is presented at the NSTAT output. NSTAT is an unlatched output that represents either the loop closure or ring trip status, depending on the device state. See Table 2 and Table 3 for more details. Loop closure threshold current (ILCTH) is set by: 250 ( VREF - VLCTH ) -------------------------------------------------- = ILCTH (mA) RLCTH ( k ) where: RLCTH is a resistor from the LCTH node to ground or a voltage source. VLCTH is ground or an external voltage source. There is a built-in hysteresis associated with the loop closure detector. The above equation describes the onhook to off-hook threshold. To help prevent false glitches, the off-hook to on-hook threshold will be a typical 20% lower than the corresponding on-hook to offhook threshold. Connect a 0.01 F to a 0.1 F capacitor from this node, LCF to VCC to filter the loop closure detector. The higher the capacitor, the quieter the filter. If loop closure filtering is not required, leave LCF open.
* Typical recommended value for CFB1 and CFB2 is less than 0.033 F.
Agere Systems Inc.
33
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Supervision (continued)
Ring Trip
Ring trip is set by the value of RS1. The ring trip threshold at the ring trip inputs is 2.5 V minimum, 3.5 V maximum. A resistor value of 400 , as shown in Figure 4, will set the ring trip current threshold to 7.5 mA typical. Ring trip is asserted upon entering the ringing mode until the second zero crossing of ringing. This is either a positive-going zero crossing (between -40 V and -30 V at -50 V VBAT) or a negative-going zero crossing (between -10 V and -20 V at -50 V VBAT). The different threshold for positive-going and negative-going zero crossings is the result of hysteresis of approximately 20 V. The act of turning on the switch may or may not produce a ringing zero crossing, therefore, there may be a delay of up to almost one cycle of ringing or 50 ms until NSTAT is high. Ring trip will not be asserted unless the ring trip threshold is exceeded for two zero crossings. This is either a positive-going zero crossing (between -40 V and -30 V at -50 V VBAT) or a negative-going zero crossing (between -10 V and -20 V at -50 V VBAT). The different threshold for positive-going and negative-going zero crossings is the result of hysteresis of approximately 20 V. Note that since the ringing voltage is monitored at RSW, one zero crossing can occur at switch turn-on depending on initial conditions. Ring trip is asserted immediately if the ring trip input is 15 V 3 V.
Switching Behavior
The solid-state ring relay in the L9311 device is able to provide either make-before-break or break-beforemake timing with respect to switching into and out of the ring mode. If switching is done directly into and out of the ring mode, the design of the L9311 will give make-before-break switching with respect to both the ring and tip side switches. To achieve break-beforemake switching, the user should via software control enter an intermediate all-off mode when switching into and out of the ring mode. The all-off state should be held a minimum of 8 ms.
Make-Before-Break Operation
The break switches are constructed from DMOS transistors. The tip side ring return is also a DMOS transistor. Because the on resistance of the break switches is less than the tip side ring return switch, the break switches are physically bigger. This implies a larger gate to source capacitance, with inherently slower switching speeds since it will take longer to charge or discharge the gate to source capacitance of the break switches (to change the state of the switch). The ring access switch is a pnpn type device. The pnpn device has inherently faster switching speeds than any of the DMOS type switches. Going from the active to ring mode, the smaller tip side ring return switch and the pnpn ring access switch will change states before the larger break switches. Thus, the ring contacts are made before the line break switches are broken: make-before-break operation. Going from the ring mode to active or scan, the natural tendency is for the smaller tip side ring return DMOS to break or open, before the larger DMOS can turn on. This would not be make-before-break operation on the tip side. Thus, circuitry is added to speed up charging of the tip break switch, to speed up the turn on of that switch to give make-before-break operation on the tip side. On the ring side, going from the ring mode to the active or scan mode, the pnpn will not turn off until the ring current drops below the hold current of the pnpn device (which is typically 500 A); this is effectively zero current for zero current turn off. This can take up to onehalf cycle of ringing to occur. With this inherent delay in switching by the pnpn ring access switch, the break switches will make contact before the ring access switch breaks contact; so again, make-before-break switching is achieved.
Ring Ground Detector
In ground start applications, a common-mode current detector is used to indicate a ring ground has occurred or an off-hook has occurred. The detection threshold is set by connecting a resistor from ICM to ground. 2350/RICM (k) = ITH (mA) Additionally, a filter capacitor across RICM will set the time constant of the detector. No hysteresis is associated with this detector.
34
Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Supervision (continued)
Make-Before-Break Operation (continued)
With the make-before-break switch, there will be a period of time (depending on ring signal frequency but measured in tens of microseconds) where all four switch contacts will be on. This means that the ring generator will be connected through the current-limited break switches to the input of the SLIC device. Current will be limited by the break switch current limit, and this will not damage the SLIC. This current may, however, cause a false glitch at the NSTAT supervision output that will need to be digitally filtered. The board designer should consider any ramifications of this state on the overall system or ring generator and battery design. The major benefit of make-before-break switching is that it will minimize any impulse noise generated during ringing cadence. In many cases when operating the switch in the make-before-break mode, no special design to switch at zero current and voltage crossing is required. Impulse noise generation when using solidstate relays is documented in the Impulse Noise and the L758X Series of Solid State Switches Application Note.
Protection
External Protection
An external overvoltage clamp is required to ensure that the off-state and on-state ratings of the solid-state break switch and solid-state ring access switch are not exceeded. The solid-state switches in the L9311 are constructed in a dielectrically isolated high-voltage technology. Because of the high device-to-device isolation that is inherent in the dielectric isolation, only a tip to ground and a ring to ground clamp is required. A tip to ring overvoltage clamp is not needed. A foldback or crowbar type device is recommended to minimize power across the solid-state switches under a fault condition. The break switches and tip return switch are constructed from DMOS transistors. Because the on resistance of the break switches is less than the tip side ring return switch, the break switches are physically bigger and have a higher current handling capability. Additionally, the break switches have a foldback characteristic which enables them to survive a higher on-state voltage (320 V) than the tip ring return switch (130 V), which does not have the foldback characteristic. (See On-State Switch I-V Characteristics section.) The ring access switch is a pnpn type device. Additionally, the ring side will see the full power ring voltage, and the tip side switch will see the power ringing voltage that is attenuated by the ringing load, subscriber loop, feed resistor, and protection resistors. Because of these differences, the protection requirements on the tip side are different from the protection requirements on the ring side. Thus, it is recommended that an asymmetrical (with respect to tip and ring) overvoltage protection scheme be used. Please contact your Agere Account Representative for a recommended protection device. Additionally, a series protection resistor with a fusible characteristic or a PTC resistor is recommended to limit current during lightning and power cross faults. A minimum 50 is recommended in tip and ring. The overall device protection is achieved through a combination of the external overvoltage and overcurrent devices, along with the integrated thermal shutdown feature, the integrated window comparator, the break switch foldback characteristic, and the dc/dynamic current-limit response of the break and tip return switches.
Break-Before-Make Operation
To achieve break-before-make, use the logic control sequence device switching as shown below. Table 19. Break-Before-Make Logic Control Sequence Device Switching State Active/Scan Disconnect (all-off) Ring Disconnect (all-off) Active/Scan Break Switches closed open open open closed Ring Switches open open closed open open Comment -- hold >8 ms -- hold >8 ms --
The advantage of break-before-make operation is that it eliminates the current spike when the ring access relay changes state. The disadvantage is that it forces an all-off state. Under inductive ringing loads, due to Ldi/dt effects, it may cause a reduction in the impulse noise performance compared to make-before-break switching.
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Protection (continued)
Active Mode Response at PT/PR
The line break switches and tip return switch are current-limited switches. The current-limit mechanism limits current through the switch to the specified dc current limit under low frequency or dc faults (power cross and/or tip-ring to ground short) and limits the current to the specified dynamic current-limit response under transient faults, such as lightning. During a lightning fault (typical 1000 V 10 x 700 s applied surge), the current-limited line break switches will pass typically 2.5 A for 0.5 s before forcing the break switches off. Once in the off state, the external protection device must ensure that the off-state voltage rating of 320 V is not exceeded. Note that the maximum differential voltage is the positive zener rating of the protection device less the battery voltage, which will appear on the line feed side of the switch. For a lower-voltage power cross, whose maximum peak voltage is below the foldback voltage breakpoint 1 (V1), the current-limited break switch will pass the current equal to the dc current limit. The current limit has a negative temperate coefficient, so as the device continues to pass current, the current limit will reduce with increasing device temperature. Ultimately, the device will reach the thermal shutdown temperature and the thermal shutdown mechanism will force an all-off state, which will stop current flow and begin device cooling. In the all-off state, the external protection device ensures that the switch off-state voltage rating is not exceeded. Once the device cools significantly, the break switches will turn on, and current will begin to flow again, until temperature forces the all-off state. This will continue until the fault condition is gone. Sneak-under surge is a voltage surge that is just below the clamping threshold of the secondary protection device. For this type of surge, when the surge voltage is below the foldback voltage breakpoint 1, operation is as described above. When the surge voltage rises above the foldback voltage breakpoint 1 (V1), but is still less than the secondary protector clamping voltage, the line break switch will crowbar into the high-impedance region of its I-V characteristic and reduce current to the specified ILIMIT2 value.
For surges whose magnitude range above the trigger of the external secondary protector, the device will operate as described above for the portion of the surge below the secondary protector trigger voltage. When the voltage rises above the external secondary protector's trigger voltage, the secondary protector will crowbar on shunting fault current to ground and reducing the tip/ring voltage seen at the device. In the active mode, the external secondary protector must ensure that the off-state voltage ratings of the ring access and ring return switch are not exceeded. Normally, the ring return switch is connected to ground on the TRING side and to the protector on the PT side; thus, the protector on the tip side in the active mode must clamp at less than 320 V. As will be seen in the Ring Mode Response at PT/PR section, during the power ringing mode, this clamp voltage on the tip side is significantly less than 320 V. Normally, the ring access switch is connected to the ring generator on the RRING side and to the protector on the PR side; thus, on one side of the switch there is the battery voltage and the peak negative ring signal, and on the PR side, the maximum turn-on voltage of the secondary protector. The ring access switch is of pnpn construction. Thus, if the off-state voltage rating of the ring access switch is exceeded, the device will crowbar into a low-impedance state. This will cause a surge into the ring generator and can cause the onstate current rating of the switch to be exceeded. The difference of the battery plus peak negative ring signal voltage less the maximum turn on of the secondary protector must not exceed the off-state voltage rating of the ring access switch. Additionally, as the secondary protector will see the power ring signal, the minimum turn-on rating of the secondary protector must be high enough to not clamp the ring signal and cause clipping distortion. The ring side will see the fullpower ring voltage, and the tip side switch will see the power ringing voltage that is attenuated by the ringing load, subscriber loop, feed resistor, and protection resistors; thus, the ring side secondary protector requires a higher clamping voltage than the tip side.
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
from residue fault current and voltages that may be passed through the switches to the actual SLIC inputs. This scheme includes an internal diode bridge voltage clamp and a battery out of range detector that forces an all-off condition if the battery voltage falls high or low out of the specified operating range. Diode Bridge The internal inputs of the actual SLIC chip are clamped to ground and to VBAT1 by an integrated diode bridge. Residual positive fault currents are clamped to ground and residual negative fault currents are clamped to battery. This implies that the battery have some current sinking capability. High common-mode currents, as may be seen under a fault condition, will be sensed and reduced to zero by the battery monitor circuit (see Battery Out of Range Detector: High [Magnitude] section). However, this detector will not prevent longitudinal current from flowing into battery. The battery supply must have the ability to sink longitudinal currents as specified in the longitudinal current capability requirement in Table 9. Battery Out of Range Detector: High (Magnitude) This feature is useful in remote power applications where a dc-dc converter with limited ability to sink current is used as the primary battery supply. Under a fault condition, the diode bridge will want to sink current into the battery. As a function of the dc-dc converter input capacitance and design, this current may cause the magnitude of supply voltage to rise and ultimately cause damage to the supply. To prevent damage to the supply, the LILAC device will monitor the battery supply voltage. If the magnitude of the battery rises above the maximum specified operating battery, the battery out of range detector will force the line break switches and ring access switches into an all-off state, and will also force the SLIC into the disconnect state. This will stop the current flow into the battery, preventing damage to the battery fault conditions. NSTAT is forced low during this mode of operation. Battery Out of Range Detector: Low (Magnitude) The LILAC device will monitor the battery supply voltage. If the magnitude of the battery drops below the minimum specified operating battery, the battery out of range detector will force the line break switches and ring access switches into an all-off state, and will also force the SLIC into the disconnect state. NSTAT is forced low during this mode of operation.
Protection (continued)
Ring Mode Response at PT/PR
In this mode, the line break switches are off and the ring access and ring return switch is on. The secondary protectors must ensure that the minimum off-state voltage rating of the line break switches is not exceeded. Note that the maximum differential voltage is the positive zener rating of the protection device less the battery voltage which will appear on the line feed side of the switch. The ring access switch is a pnpn type switch. This switch has no internal current limiting. Thus, through external current limit, the user must ensure that the surge ratings (both dynamic and dc for lightning and power cross faults) are not exceeded. A minimum 400 ring feed resistor is recommended. This resistor also will set the ring trip threshold. See the Ring Trip section within the Supervision section of this data sheet. During a lightning fault (typical 1000 V 10 x 700 s applied surge), the current-limited tip return switch will pass, typically 2.5 A for 0.5 s before forcing the switch off. Once in the off state, the external protection device must ensure that the off-state voltage rating of 320 V is not exceeded. For power cross for lower-voltage faults, the tip side power ringing return switch will behave like the line break switches. However, this switch does not have the foldback clamping feature that is included in the line break switches; thus, in the on state, the voltage seen by the tip side power ringing return switch before damage is less than the line break switches. The on-state voltage of the line break switches can go up to the offstate voltage rating. The tip side power ringing return voltage should see less than 130 V in the on state. Thus, the secondary protector on the tip side should have a maximum crowbar voltage of 130 V. With typical protection device tolerance, this implies a minimum clamping voltage of 100 V. The users should ensure, based on minimum loop length, ringing load, and peak ring signal voltage, that the ring signal is not distorted by the (lower) voltage rating of the tip-side protector.
Internal Tertiary Protection
The external secondary protector and switch current limit protect the 320 V high-voltage switches from lightning and power cross conditions. Integrated into the LILAC IC is an internal tertiary protection scheme that is meant to protect the 90 V SLIC portion of the device
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Special Functions
Line Test
The L9311 provides line test capability. Through a series of integrated analog switches, in the test mode, an analog voltage proportional to the dc tip to ground voltage, dc ring to ground voltage, the differential dc tip to ring voltage may be generated at the SLIC TESTLEV output. Additionally an analog voltage proportional to the dc tip to ground current, dc ring to ground current, the differential dc tip to ring current may also be generated at the SLIC TESTLEV. Figure 2 shows the architecture of the integrated test switches. The test switches are configured via the logic input table to provide voltage measurements, tip to ground, ring to ground and tip to ring. A voltage that is proportional to the ac tip/ring current appears at the VITR output; thus, for ac current measurements, the test switches apply the VITR output to the TESTLEV output. A voltage that is proportional to the ac plus dc tip/ring current appears at the VTX output; thus, for dc current measurements, the test switches apply the VTX output to the TESTLEV output, with TESTSIG input grounded. Differential tip to ring current is achieved via the logic truth table. Additionally, individual control of the line break switches allows tip to ground current measurements (tip break switch closed, ring break switch open, tip amp state) or ring to ground current measurements (tip break switch open, ring break switch closed, ring amp state). An analog ac test tone may also be applied to a test input TESTSIG. TESTSIG input is active upon entering a test state and remains active until leaving the test
mode. Using this feature, a voltage proportional to ac tip to ground voltage, ac ring to ground voltage, the differential ac tip to ring, the ac tip to ground current, ac ring to ground current, the differential ac tip to ring current may also be generated at the SLIC TESTLEV. By varying the frequency of the applied test tone, parameters such as line capacitance may be measured. If the codec can accommodate self-test features, the L9311 can be configured to operate in this mode. During the test modes. The L9311 receive path is active, thus a test tone may be applied at the RCVN/RCVP inputs, through the codec, via a PCM input. In this mode of operation, couple TESTLEV, not VITR, to the codec. All measurements that appear at the TESTLEV output are referenced to the internal VREF voltage of the device. For that reason, there is a test mode in which VREF itself will appear at the TESTLEV output. When making a voltage measurement, first measure VREF and subtract VREF from VTESTLEV. When making a current measurement, open the line break switches and measure VTESTLEV. This value is then subtracted from the VTESTLEV that is seen during the actual measurement. Note that due to internal biasing of the line break switches, the value seen at VTESTLEV with the line break switches open will be less than the value seen with the line break switches closed under on-hook (open-loop) conditions. TESTSIG should be externally connected to the device's VREF if it is not used during a test condition. This may be done by a high-impedance pull-up resistor. Additionally TESTSIG should be ac-coupled to the test signal generator.
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Special Functions (continued)
Line Test (continued)
Table 20 shows design equations to measure the various line voltages and currents. Table 20. TESTLEV Output Options Test Mode Test Off VREF -- Unity follower on VREF. This is the voltage measurement calibration state, use the VREF state in the secondary control state table. (VTIP - VRING) = 75 (1 - 0.0075 |VTL|) Difference amp. x VTL VTL = VTESTLEV - (VREF + VOFFSET) VTIP = -75 (1 - 0.0075 |VTL|) x VTL + Inverting amp. VREF + VOFFSET VTL = VTESTLEV - (VREF + VOFFSET) VRING = -75 (1 - 0.0075 |VTL|) x VTL Inverting amp. + VREF + VOFFSET VTL = VTESTLEV - (VREF + VOFFSET) Unity follower on VTX close to VREF + VAXOFFVTESTLEV = VZEROCUR SET + VOFFSET. This is the current measurement calibration state. In the secondary control state table, use tip amp or ring amp for single-ended current measurement calibration. Use tip and ring amp for differential current measurement calibration. Do not use the disconnect mode for current calibration. VTESTLEV = 20 V/A x ITIP-to-RING + VZE- Differential current.
ROCUR
Relationship High Impedance VTESTLEV = VREF + VOFFSET
Comments
Tip-to-Ring Voltage
Tip-to-Ground Voltage
Ring-to-Ground Voltage
VTX, Zero Current (tip open, ring open)
VTX, dc Current Tip/Ring (tip closed, ring closed) VTX, dc Current Ring Ground (tip closed, ring open) VTX, dc Current Ring Ground (tip open, ring closed) VITR, Zero Current (tip open, ring open)
VTESTLEV = 10 V/A x ITIP-to-RING + VZE- Single-ended voltage.
ROCUR
VTESTLEV = -10 V/A x ITIP-to-RING + VZEROCUR VTESTLEV = VZAC
Single-ended voltage.
VITR, ac Current (tip closed, ring closed)
VTESTLEV = 300 V/A x ITIP-to-RING + VZAC
Unbuffered output of VITR close to VREF + VAXOFFSET + VACOFFSET. This is the current measurement calibration state. In the secondary control state table, use tip amp or ring amp for single-ended current measurement calibration, use tip and ring amp for differential current measurement calibration. Do not use the disconnect mode for current calibration. --
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
ac Applications
ac Parameters
There are four key ac design parameters. Termination impedance is the impedance looking into the 2-wire port of the line card. It is set to match the impedance of the telephone loop in order to minimize echo return to the telephone set. Transmit gain is measured from the 2-wire port to the PCM highway, while receive gain is done from the PCM highway to the transmit port. Transmit and receive gains may be specified in terms of an actual gain, or in terms of a transmission level point (TLP), that is the actual ac transmission level in dBm. Finally, the hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port.
Third-Generation Codecs. This class of devices includes all ac parameters set digitally under microprocessor control. Depending on the device, it may or may not have data control latches. Additional functionality sometimes offered includes tone plant generation and reception, PPM generation, test algorithms, and echo cancellation. Again, this type of codec may be +5 V only or 5 V operation, single quad or 16-channel, and -law/A-law or 16-bit linear coding selectable. Examples of this type of codec are the Agere T8536/7 (5 V only, quad, standard features), T8533/4 (5 V only, quad with echo cancellation), and the T8531/36 (5 V only 16channel with self-test).
Codec Types
At this point in the design, the codec needs to be selected. The interface network between the SLIC and codec can then be designed. Below is a brief codec feature summary. First-Generation Codecs. These perform the basic filtering, A/D (transmit), D/A (receive), and -law/A-law companding. They all have an op amp in front of the A/D converter for transmit gain setting and hybrid balance (cancellation at the summing node). Depending on the type, some have differential analog input stages, differential analog output stages, +5 V only or 5 V operation, and -law/A-law selectability. These are available in single and quad designs. This type of codec requires continuous time analog filtering via external resistor/capacitor networks to set the ac design parameters. An example of this type of codec is the Agere T7504 quad 5 V only codec. This type of codec tends to be the most economical in terms of piece part price, but tends to require more external components than a third-generation codec. Further, ac parameters are fixed by the external R/C network so software control of ac parameters is difficult.
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
thesize the higher termination impedances. Further, the termination that is achieved will be far less than what is calculated by assuming a short for SLIC output to SLIC input. In the receive direction, in order to control echo, the gain is typically a loss, which requires a loss network at the SLIC RCVN/RCVP inputs, which will reduce the amount of gain that is available for termination impedance. For this reason, a high-gain SLIC is required with a first-generation codec. With a third-generation codec, the line card designer has different concerns. To design the ac interface, the designer must first decide upon all termination impedance, hybrid balances, and TLP requirements that the line card must meet. In the transmit direction, the only concern is that the SLIC does not provide a signal that is too large and overloads the codec input. Thus, for the highest TLP that is being designed to, given the SLIC gain, the designer, as a function of voiceband frequency, must ensure the codec is not overloaded. With a given TLP and a given SLIC gain, if the signal will cause a codec overload, the designer must insert some sort of loss, typically a resistor divider, between the SLIC output and codec input. In the receive direction, the issue is to optimize the S/N. Again, the designer must consider all the considered TLPs. The idea, for all desired TLPs, is to run the codec at or as close as possible to its maximum output signal, to optimize the S/N. Remember, noise floor is constant, so the larger the signal from the codec, the better the S/N. The problem is if the codec is feeding a high-gain SLIC, either an external resistor divider is needed to knock the gain down to meet the TLP requirements, or the codec is not operated near maximum signal levels, thus compromising the S/N.
ac Applications (continued)
ac Interface Network
The ac interface network between the L9311 and the codec will vary depending on the codec selected. With a first-generation codec, the interface between the L9311 and codec actually sets the ac parameters. With a third-generation codec, all ac parameters are set digitally, internal to the codec; thus, the interface between the L9311 and this type of codec is designed to avoid overload at the codec input in the transmit direction, and to optimize signal to noise ratio (S/N) in the receive direction. Because the design requirements are very different with a first- or third-generation codec, the L9311 is offered with two different receive gains. Each receive gain was chosen to optimize, in terms of external components required, the ac interface between the L9311 and codec. With a first-generation codec, the termination impedance is set by providing gain shaping through a feedback network from the SLIC VITR output to the SLIC RCVN/RCVP inputs. The L9311 provides a transconductance from T/R to VITR in the transmit direction and a single ended to differential gain in the receive direction, from either RCVN or RCVP to T/R. Assuming a short from VITR to RCVN or RCVP, the maximum impedance that is seen looking into the SLIC is the product of the SLIC transconductance times the SLIC receive gain, plus the protection resistors. The various specified termination impedance can range over the voiceband as low as 300 up to over 1000 . Thus, if the SLIC gains are too low, it will be impossible to syn-
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
ac Applications (continued)
ac Interface Network (continued)
Thus, it appears the solution is to have a SLIC with a low gain, especially in the receive direction. This will allow the codec to operate near its maximum output signal (to optimize S/N), without an external resistor divider (to minimize cost). Note also that some third-generation codecs require the designer to provide an inherent resistive termination via external networks. The codec will then provide gain shaping, as a function of frequency, to meet the return loss requirements. Further stability issues may add external components or excessive ground plane requirements to the design. To meet the unique requirements of both types of codecs, the L9311 offers two receive gain choices. These receive gains are mask programmable at the factory and are offered as two different code variations. For interface with a first-generation codec, the L9311 is offered with a receive gain of 8. For interface with a third-generation codec, the L9311 is offered with a receive gain of 2. In either case, the transconductance in the transmit direction, or the transmit gain, is 300 . This selection of receive gain gives the designer the flexibility to maximize performance and minimize external components, regardless of the type of codec chosen.
First-Generation Codec ac Interface Network
Termination impedance may be specified as purely resistive or complex, that is, some combination of resistors and capacitors that causes the impedance to vary with frequency. The design for a pure resistive termination, such as 600 , does not vary with frequency, so it is somewhat more straightforward than a complex termination design. For this reason, the case of a resistive design and complex design will be shown separately.
First-Generation Codec ac Interface Network: Resistive Termination
The following reference circuit shows the complete SLIC schematic for interface to the Agere T7504 firstgeneration codec for a resistive termination impedance. For this example, the ac interface was designed for a 600 resistive termination and hybrid balance with transmit gain and receive gain set to 0 dBm. Also, this example illustrates the device with a single battery operation, fixed current limit, and fixed loop closure threshold. This is a lower feature application example. Resistor RGN is optional. It compensates for any mismatch of input bias voltage at the RCVN/RCVP inputs. If it is not used, there may be a slight offset at tip and ring due to mismatch of input bias voltage at the RCVN/RCVP inputs. It is very common to simply tie RCVN directly to ground in this particular mode of operation. If used, to calculate RGN, the impedance from RCVN to ac ground should equal the impedance from RCVP to ac ground.
Design Tools
The following examples illustrate the design techniques/equations followed to design the ac interface with a first- or third-generation codec for both a resistive and complex design. To aid the line circuit design, Agere has available Windows*-based spreadsheets to do the individual component calculations. Further, Agere has available PSPICE models for circuit simulation and verification. Consult your Agere Account Representative to obtain these design tools.
* Windows is a registered trademark of Microsoft Corporation. PSPICE is a registered trademark of MicroSim Corporation.
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
ac Applications (continued)
First-Generation Codec ac Interface Network: Resistive Termination (continued)
RX VGSX
-0.300 V/mA RT6 VITR BREAK SWITCH 18 RCVN VREF RCVP RGP AV = -1 RING 18 20 L9311 VREF 1/4 T7504 CODEC
12-3580C (F)
VFXIN - VFXIP + 2.4 V VFR
ZT/R
RP TIP
20 AV = 1
- AV = 4 +
RT3 RHB1 RRCV
VS
IT/R + ZT VT/R - RP
BREAK SWITCH
CURRENT SENSE
Figure 15. ac Equivalent Circuit
Example 1, Real Termination The following design equations refer to the circuit in Figure 15. Use these to synthesize real termination impedance. Termination Impedance: VT/R ZT = ------------ IT/R ZT = 76 2400 + 2 RP + ---------------------------------RT3 RT3 1 + -------- + ----------RGP RRCV
Transmit Gain: gtx = VGSX ---------VT/R
gtx =
- RX x -------300 -------RT6
ZT/R
Hybrid Balance: RX hbal = 20 log -------------- - gtx x grcv RHB1 VGSX hbal = 20 log -------------- VFR To optimize the hybrid balance, the sum of the currents at the VFX input of the codec op amp should be set to 0. The expression for ZHB becomes:
Receive Gain: VT/R grcv = ----------VFR grcv =
-----------------------------------------------------------------ZT 1 + RRCV + RRCV 1 + -------- - ----------- -----------
RT3 RGP ZT/R
8
RHB ( k ) =
RX -----------------gtx x grcv
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
ac Applications (continued)
First-Generation Codec ac Interface Network: Resistive Termination (continued)
Example 1, Real Termination (continued)
VBAT1
VCC CCC 0.1 F
VDD
A
CVBAT1 0.1 F
CDD 0.1 F
D
VBAT RINGING SOURCE RG1 FUSIBLE OR PTC 50 180 V--330 V SECONDARY PROTECTOR 100 V--130 V SECONDARY PROTECTOR 50 FUSIBLE OR PTC RLCTH 59 k RVPROG 33.2 k RVREF 64.9 k 400 CRTI RRTF 0.1 F 1 M
VBAT2/ VBAT1 BGND VCC PWR TRING RRING
AGND VDD
DGND ICM RGDET ITR VTX RGX 6.34 k CTX 0.15 F RX 100 k RT6 49.9 k VITR RT3 140 k RRCV 100 k CC1 0.33 F - VFXIN RHB1 100 k + +2.4 V VFRO CC2 0.1 F DR FSE FSEP MCLK ASEL RGN 28.3 k VREF 1/4 T7504 CODEC SYNC AND CLOCK CONTROL INPUTS DX PCM HIGHWAY GSX
RSW TXI RTS PR
L9311
(GAIN OF 8)
RCVP
PT OVH (DEFAULT OVERHEAD) LCTH (10 mA) RCVN FB2 VPROG (ILIMIT = 40 mA) FB1 LCF
B3 B2 B1 B0 NSTAT RESET LATCH TESTLEV TESTSIG
RGP 43.2 k VREF
VREF CF2
CF1
CF2 0.015 F
VREF
MULTIPLEXED DATA BUS TO/FROM MICROPROCESSOR
PER-LINE TO/FROM MICROPROCESSOR
12-3521f (F)
Notes: Termination impedance = 600 . Hybrid balance = 600 . Tx = 0 dBm. Rx = 0 dBm.
Figure 16. Agere T7504 First-Generation Codec Resistive Termination, Single Battery Operation
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
ac Applications (continued)
First-Generation Codec ac Interface Network: Resistive Termination (continued)
Example 1, Real Termination (continued) Table 21. L9311 Parts List for Agere T7504 First-Generation Codec Resistive Termination, Single Battery Operation Name Value Tolerance 1% 1% -- -- 20% 20% 20% 20% 1% 1% 20% 1% 5% 1% 1% 20% 20% 20% 1% 1% 1% 1% 1% 1% 1% Rating Fusible or PTC Fusible or PTC -- -- 100 V 10 V 10 V 100 V Protection resistor. Protection resistor. Ring-side secondary protector. Tip-side secondary protector. Filter capacitor. Filter capacitor. Filter capacitor. Filter capacitor. Function
Fault Protection RPR 50 RPT 50
Protector* 180 V to 320 V Protector* 100 V to 130 V Power Supply CVBAT1 0.1 F CCC 0.1 F CDD 0.1 F CF2 0.015 F dc Profile RVPROG 33.2 k RVREF 64.9 k Supervision CRTF 0.1 F RRTF 1 M RRS1 400 RLCTH 59 k ac Interface RGX 6.34 k CTX 0.15 F CC1 0.33 F CC2 0.1 F RT3 140 k RT6 RX RHB RRCV RGP RGN Optional 49.9 k 100 k 100 k 100 k 43.2 k 28.3 k
1/16 W With RVREF fix dc current limit. 1/16 W With RVPROG fix dc current limit. 100 V 1/16 W 2W 1/16 W 1/16 W 10 V 10 V 10 V 1/16 W 1/16 W 1/16 W 1/16 W 1/16 W 1/16 W 1/16 W Ring trip filter capacitor. Ring trip filter resistor. Sets ring trip threshold. With RVREF, fix loop supervision threshold. Sets T/R to VITR transconductance. ac/dc separation. dc blocking capacitor. dc blocking capacitor. With RGP and RRCV, sets termination impedance and receive gain. With RX, sets transmit gain. With RT6, sets transmit gain. With RX, sets hybrid balance. With RGP and RT3, sets termination impedance and receive gain. With RRCV and RT3, sets termination impedance and receive gain. Optional. Compensates for input offset at RCVN/RCVP.
* See your Agere Account Representative for a recommended secondary protection device.
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
ac Applications (continued)
Third-Generation Codec ac Interface Network: Complex Termination
The following reference circuit shows the complete SLIC schematic for interface to the Agere T8536 third-generation. All ac parameters are programmed by the T8536. Note this codec differentiates itself in that no external components are required in the ac interface to provide a dc termination impedance or for stability. Also, this example illustrates the device using the battery switch with multiple battery operation and programmable overhead, current limit, and loop closure threshold. Please see the T8535/6 data sheet for information on coefficient programming.
VBAT2 VBAT1
VCC CCC 0.1 F
VDD
A
CVBAT1 CVBAT2 0.1 F 0.1 F
CDD 0.1 F
D
VBAT2/ VBAT1 BGND VCC PWR TRING VBAT RRING RINGING SOURCE RS1 400 CRTS RRTF 0.1 F 1 M RSW RTS PR
AGND VDD
DGND ICM RGDET
ITR RGX 6.34 k VTX CTX 0.15 F TXI CC1 0.33 F VITR RCVP RCVN RCIN 20 M VFXIN VFROP VFRON DX0 DR0 DX1 DR1 PCM HIGHWAY
FUSIBLE OR PTC 50
180 V--330 V SECONDARY PROTECTOR
L9311
(GAIN OF 2)
NSTAT LATCH
T8536
SLIC0a SLIC5a B3 B2 SLIC4a SLIC3a SLIC2a SLIC1a FB2 FB1 LCF
100 V--130 V SECONDARY PROTECTOR 50 PT FUSIBLE OR PTC OVH FROM PROGRAMMABLE VOLTAGE SOURCE VPROG RVPROG LCTH VREF
CF2 CF1 RESET TESTLEV TESTSIG
FS BCLK DGND
SYNC AND CLOCK
B1 B0
CVDD 0.1 F VDD VDD
CF2 0.015 F
VREF
PER-LINE TO/FROM MICROPROCESSOR
12-3527g(F)
Figure 17. L9311 for Agere T8536 Third-Generation Codec, Dual Battery Operation, ac and dc Parameters, Fully Programmable
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
ac Applications (continued)
Third-Generation Codec ac Interface Network: Complex Termination (continued)
Table 22. L9311 Parts List for Agere T8536 Third-Generation Codec, Dual Battery Operation, ac and dc Parameters, Fully Programmable Name Fault Protection RPR RPT Protector* Protector* Power Supply Diode CVBAT1 CVBAT2 CCC CDD CF2 Supervision CRTF RRTF RRS1 ac Interface RGX RCIN CTX CC1 Value 50 50 180 V to 320 V 100 V to 130 V 1N4004 0.1 F 0.1 F 0.1 F 0.1 F 0.015 F 0.1 F 1 M 400 6.34 k 20 M 0.15 F 0.33 F Tolerance 1% 1% -- -- -- 20% 20% 20% 20% 20% 20% 1% 5% 1% 5% 20% 20% Rating Function
Fusible or Protection resistor. PTC Fusible or Protection resistor. PTC -- Ring-side secondary protector. -- Tip-side secondary protector. -- 100 V 50 V 10 V 10 V 100 V 100 V 1/16 W 2W 1/16 W 1/16 W 10 V 10 V Reverse battery current. Filter capacitor. Filter capacitor. Filter capacitor. Filter capacitor. Filter capacitor. Ring trip filter capacitor. Ring trip filter resistor. Sets ring trip threshold. Sets T/R to VITR transconductance. dc bias. ac/dc separation. dc blocking capacitor.
* See your Agere Account Representative for a recommended secondary protection device.
Agere Systems Inc.
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L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Data Sheet July 2001
Outline Diagram
44-Pin PLCC
17.65 MAX 16.66 MAX PIN #1 IDENTIFIER ZONE
6
1
40
7
39
16.66 MAX 17.65 MAX
17
29
18
28
4.57 MAX SEATING PLANE 1.27 TYP 0.53 MAX 0.51 MIN TYP 0.10
5-2506F
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Agere Systems Inc.
Data Sheet July 2001
L9311 Full-Feature SLIC with High Longitudinal Balance, Ringing Relay, and GR-909 Test Access
Ordering Information
Device Part Number LUCL9311AP-D LUCL9311AP-DT Package 44-Pin PLCC, Dry-bagged 44-Pin PLCC, Dry-bagged, Tape and Reel 44-Pin PLCC, Dry-bagged 44-Pin PLCC, Dry-bagged, Tape and Reel Comcode 108555491 108555509
LUCL9311GP-D LUCL9311GP-DT
108555533 108555541
Agere Systems Inc.
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For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@micro.lucent.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright (c) 2001 Agere Systems Inc. All Rights Reserved
July 2001 DS01-191ALC (Replaces DS01-169ALC)

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